Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 7/15/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

F-Tile Transceiver Reference Clock Specifications

Table 55.  F-Tile FHT Reference Clock Requirements For specification status, see the Data Sheet Status table
Parameter Description Condition Min Typical Max Unit
Frequency Reference clock frequency — 100 156.25 200 MHz
Frequency accuracy Frequency accuracy of the reference clock, including temperature variability, aging, and initial variation — — — ±100 ppm
Single sideband phase noise Measured SSB phase noise must be smaller than phase noise mask92 10 kHz — — –130 dB
100 kHz — — –138 dB
500 kHz — — –138 dB
3 MHz — — –140 dB
10 MHz — — –144 dB
20 MHz — — –146 dB
1 GHz — — –146 93 dB
Integrated RMS jitter Integrated over 10 kHz – 20 MHz, include spurious — — — 522 fs
Table 56.  F-Tile FHT Reference Clocks Input Specifications

LVDS is recommended with on-board 100 nF AC-coupling capacitor.

For specification status, see the Data Sheet Status table

Parameter Description Condition Min Typical Max Unit
TREF-DUTY Duty cycle — 45 50 55 %
TREF-RISE/FALL Rising and falling edge rate 20% – 80% 40 — 300 ps
TREF-SINGLEEND-SKEW Skew between REFCLKP and REFCLKN — — — 5 ps
ZREF-SINGLEEND-DC Reference clock input impedance – terminated mode — 40 50 60 Ω
VREFIN-SE-PP Input reference clock single-ended peak-to-peak voltage — 200 — 510 mV
VREFIN-CM-AC Input reference clock common-mode voltage when AC-coupled on board  — Set on-chip (no user access) —
VREFIN-IL-DC Input reference clock input low voltage when DC-coupled on board — 0.1 — — V
VREFIN-IH-DC Input reference clock input high voltage when DC-coupled on board  — — — 0.9 V
Table 57.  F-Tile FGT Reference Clock Input Specifications For specification status, see the Data Sheet Status table
Parameter Description Condition Min Typical Max Unit
Supported I/O standards — Dedicated reference clock pin CML, HCSL
FREF Reference clock operating frequency — 10094 — 380 MHz
TREF-DUTY Duty cycle — 45 50 55 %
TREF-RISE/FALL Rising and falling edge rate 20% – 80% — — 0.15 × Tref_period ps
TREF-SINGLEEND-SKEW Skew between REFCLKP and REFCLKN — — — 50 ps
ZREF-DIFF-DC 95 Reference clock differential input impedance – terminated mode — 80 100 120 Ω
VREFIN-DIFF 96 Input reference clock differential peak-to-peak voltage — 0.6 1.2 1.7 V
VREFIN-IL-DC Input reference clock input low voltage when DC-coupled on board — 0 — — V
VREFIN-IH-DC Input reference clock input high voltage when DC-coupled on board    — — — 1 V
VREFIN-CM-AC Input reference clock common-mode voltage when AC-coupled on board — Set on-chip (no user access) V
VREFIN-CM-DC Input reference clock common-mode voltage when DC-coupled on board — 0.2 — 0.8 V
PNREF-SSB (156.25 MHz) Reference clock measured single sideband phase noise mask including spurs must be smaller than phase noise mask97 10 kHz — — –130 dBc/Hz
100 kHz — — –138 dBc/Hz
500 kHz — — –138 dBc/Hz
3 MHz — — –140 dBc/Hz
10 MHz — — –144 dBc/Hz
20 MHz — — –146 dBc/Hz
1 GHz — — –146 dBc/Hz
VREFIN-RJ-RMS RMS jitter integrated from 10 kHz – 20 MHz including spurs — — — 522 fs
VREFIN-PPM-ERROR Reference clock frequency error — –350 + SSC — +350 + SSC ppm
Figure 4. Simplified F-Tile FGT Reference Clock Input Buffer
Table 58.  F-Tile FGT Reference Clock Output Driver Specifications For specification status, see the Data Sheet Status table
Parameter Description Condition Min Typical Max Unit
FREF_OUT Reference clock operating frequency — 25 — 800 MHz
TREF-DUTY_OUT Duty cycle — 45 50 55 %
TREF-RISE_OUT/FALL_OUT Rising and falling edge rate 20% – 80% — — 0.15 × Tref_period ps
TREF-SINGLEEND-SKEW Skew between REFCLKP and REFCLKN — — — 50 ps
ZREF-DIFF-DC_OUT Reference clock differential output impedance – terminated mode — 80 100 120 Ω
VREFIN-DIFF-AC_OUT Output reference clock differential peak to peak voltage when AC-coupled on board — 0.9 1 1.1 V
VREFIN-CM-OUT 98 Output reference clock common-mode — 0.45 0.5 0.55 V
92 Add an offset of 20 × log10(Fclk/156.25 MHz) dB to mask values, where Fclk is reference clock frequency.
93 The phase noise mask requirement between 20 MHz and 1 GHz excludes any harmonics power of the fundamental clock.
94 This value is 100 MHz for down SSC (Spread Spectrum Clocking) clocking. This value can also be 25 MHz for HDMI rate of less than 1 Gbps.
95 These termination resistors are part of the reference clock input buffer on-chip, and are always present and no external termination or DC biasing is needed if AC-coupled on board. If DC-coupled on board, external biasing is not required unless a signaling standard other than differential 100 Ω termination is required.
96 LVDS is recommended with on-board AC-coupling and subject to 0.6 V ≤ VREFIN-DIFF ≤ 1.7 V.
97 Add an offset of 20 × log10(Fclk/156.25 MHz) dB to mask values, where Fclk is reference clock frequency.
98 If your far-end differential termination is comprised of two 50 Ω terminations to GND, the common-mode voltage is nominally 250 mV. If your far-end differential termination is comprised of a single 100 Ω differential termination between the P and N signals, the common-mode voltage is nominally 500 mV.
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