Visible to Intel only — GUID: cfe1657772076387
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: cfe1657772076387
Ixiasoft
Absolute Maximum Ratings
This section defines the maximum operating conditions. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.
CAUTION:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Symbol | Description | Condition | Minimum | Maximum | Unit |
---|---|---|---|---|---|
VCC | Core voltage power supply | SmartVID1 : –1V, –2V, –3V, –3E | –0.5 | 1.21 | V |
VCCP | Periphery circuitry power supply | SmartVID1: –1V, –2V, –3V, –3E | –0.5 | 1.21 | V |
VCCPT | Power supply for I/O PLL and I/O pre-driver | — | –0.5 | 2.08 | V |
VCCRCORE | CRAM power supply | — | –0.5 | 1.64 | V |
VCCH | Transceiver digital power supply | Devices with R-Tile and F-Tile | –0.5 | 1.07 | V |
Devices with F-Tile only | –0.5 | 1.07 | V | ||
VCCH_SDM | SDM block transceiver digital power sense | Devices with R-Tile and F-Tile | –0.5 | 1.21 | V |
Device with F-Tile only | –0.5 | 1.07 | V | ||
VCCIO_PIO_SDM | SDM block I/O bank power sense of bank 3A | — | –0.5 | 2.01 | V |
VCCIO_SDM | SDM block configuration pins power supply | — | –0.5 | 2.08 | V |
VCCL_SDM | SDM block core voltage power supply | — | –0.5 | 1.07 | V |
VCCFUSEWR_SDM | SDM block fuse writing power supply | — | –0.5 | 2.4 | V |
VCCPLLDIG_SDM | SDM block PLL digital power supply | — | –0.5 | 1.07 | V |
VCCPLL_SDM | SDM block PLL analog power supply | — | –0.5 | 2.08 | V |
VCCBAT | Battery back-up power supply (For design security volatile key register) | — | –0.5 | 2.34 | V |
VCCADC | ADC voltage sensor power supply | — | –0.5 | 2.08 | V |
VCCIO_PIO | I/O bank power supply | VCCIO_PIO = 1.05 V | –0.5 | 1.43 | V |
VCCIO_PIO = 1.1 V | –0.5 | 1.5 | V | ||
VCCIO_PIO = 1.2 V | –0.5 | 1.64 | V | ||
VCCIO_PIO = 1.3 V | –0.5 | 1.74 | V | ||
VCCIO_UIB | Power supply for the Universal Interface Bus between the core and embedded HBM2E memory | — | –0.5 | 1.6 | V |
VCCM_PUMP_HBM | HBM2E power supply | — | –0.5 | 3 | V |
VCCIO_NOC | NOC configuration pins power supply | — | –0.5 | 2.08 | V |
VCCPLL_NOC | NOC PLL analog power supply | — | –0.5 | 2.08 | V |
VCCPLLDIG_NOC | NOC PLL digital power supply | — | –0.5 | 1.07 | V |
VCCLPLL_NOC | NOC PLL core voltage power supply | — | –0.5 | 1.07 | V |
VCCH_GXR | Transceiver analog high voltage power | R-Tile devices | –0.5 | 2.03 | V |
VCCRT_GXR | Transceiver analog power supply | R-Tile devices | –0.5 | 1.33 | V |
VCCED_GXR | Transceiver digital power supply | R-Tile devices | –0.5 | 1.21 | V |
VCCE_PLL_GXR | PLLs power supply | R-Tile devices | –0.5 | 1.33 | V |
VCCE_DTS_GXR | DTS power supply | R-Tile devices | –0.5 | 1.33 | V |
VCCCLK_GXR | R-Tile reference clock power supply | R-Tile devices | –0.5 | 1.34 | V |
VCCHFUSE_GXR | R-Tile efuse power supply | R-Tile devices | –0.5 | 1.34 | V |
VCC_HSSI_GXR | R-Tile digital signal power supply | R-Tile devices | –0.5 | 1.21 | V |
VCC_HSSI_GXF | F-Tile digital signal power supply | F-Tile devices | –0.5 | 1.07 | V |
VCCFUSECORE_GXF | F-Tile fuse writing power supply | F-Tile devices | –0.5 | 1.37 | V |
VCCFUSEWR_GXF | F-Tile efuse power supply | F-Tile devices | –0.5 | 1.37 | V |
VCCCLK_GXF | F-Tile reference clock power supply | F-Tile devices | –0.5 | 2.04 | V |
VCCERT1_FHT_GXF | FHT analog core supply 1 | F-Tile devices | –0.5 | 1.33 | V |
VCCERT2_FHT_GXF | FHT analog core supply 2 | F-Tile devices | –0.5 | 1.33 | V |
VCCEHT_FHT_GXF | FHT high voltage power supply for analog circuit | F-Tile devices | –0.5 | 1.99 | V |
VCCERT_FGT_GXF | FGT analog core supply | F-Tile devices | –0.5 | 1.34 | V |
VCCH_FGT_GXF | FGT analog I/O power supply | F-Tile devices | –0.5 | 2.04 | V |
VCCERT_GXF_COMBINE | F-Tile reference clock power supply | F-Tile devices | –0.5 | 1.33 | V |
VCCL_HPS | HPS core voltage and periphery circuitry power supply | — | –0.5 | 1.21 | V |
VCCPLLDIG_HPS | HPS PLL digital power supply | — | –0.5 | 1.21 | V |
VCCPLL_HPS | HPS PLL analog power supply | — | –0.5 | 2.08 | V |
VCCIO_HPS | HPS I/O buffers power supply | — | –0.5 | 2.08 | V |
VI | DC input voltage | VCCIO_PIO = 1.05 V2 3 | –0.3 | VCCIO_PIO(MAX) + 0.25 | V |
VCCIO_PIO = 1.1 V2 3 | –0.3 | VCCIO_PIO(MAX) + 0.25 | V | ||
VCCIO_PIO = 1.2 V2 3 | –0.3 | VCCIO_PIO(MAX) + 0.25 | V | ||
VCCIO_PIO = 1.3 V2 3 | –0.3 | VCCIO_PIO(MAX) + 0.25 | V | ||
VCCIO_SDM = 1.8 V | –0.3 | VCCIO_SDM(MAX) + 0.3 | V | ||
VCCIO_HPS = 1.8 V | –0.3 | VCCIO_HPS(MAX) + 0.3 | V | ||
IOUT 4 5 | DC output current per pin | VCCIO_PIO = 1.05 V, 1.1 V, 1.2 V, 1.3 V 6 7 | –7.5 | 7.5 | mA |
VCCIO_SDM, VCCIO_HPS = 1.8 V 8 | –20 | 20 | mA | ||
TJ | Absolute junction temperature | — | –55 | 125 | °C |
TSTG | Storage temperature | — | –55 | 150 | °C |
Related Information
1 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
2 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
3 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI (DC) for the LVCMOS input can go up to VCCIO_PIO(MAX) + 0.3 V.
4 Total current per I/O bank must not exceed 100 mA.
5 Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os.
6 The maximum current allowed through any GPIO-B bank pin during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed 1.2 V or the VCCIO_PIO supply rail of the bank where the I/O pin resides in, whichever is the lower voltage. While this device is not turned on, the I/O pin should be tri-stated or not driven with any external voltages.
7 The DC output current per pin may exceed 7.5 mA with a duration limit. For more details, refer to the related information.
8 The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HPS or VCCIO_SDM supply rail of the bank where the I/O pin resides in.