Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

F-Tile Electrical Compliance

Table 63.  F-Tile FHT Supported Electrical Compliance List For specification status, see the Data Sheet Status table
Specification/Clause Protocol Encoding Lane Rate (Gbps)
IEEE 802.3-2022

IEEE 802.3ck-2022

 400GAUI-4 PAM4 106.25
200GAUI-2 PAM4 106.25
200GAUI-4 PAM4 53.125
IEEE 802.3-2022 100GAUI-1 PAM4 106.25
100GAUI-2 PAM4 53.125
100GAUI-4 NRZ 25.78125
50GAUI-1 PAM4 53.125
50GAUI-2 NRZ 25.78125
IEEE 802.3-2022 25GAUI-1 NRZ 25.78125
IEEE 802.3ck-2022 163/162 400GBASE-KR4/CR4 PAM4 106.25
200GBASE-KR2/CR2 PAM4 106.25
100GBASE-KR/CR PAM4 106.25
CEI 4.0/5.0 OIF-CEI-112G VSR/MR/LR PAM4 96 – 116
OIF-CEI-56G VSR/MR PAM4 48 – 58
OIF-CEI-28G VSR/SR/MR NRZ 24 – 29
OIF-25G NRZ 24 – 29
Table 64.  F-Tile FGT Supported Electrical Compliance List For specification status, see the Data Sheet Status table
Specification/Clause Protocol109 Encoding Lane Rate (Gbps)
IEEE 802.3-2022 400GAUI-8 PAM4 53.125
400GAUI-16 NRZ 26.5625
200GAUI-4 PAM4 53.125
200GAUI-8 NRZ 26.5625
IEEE 802.3-2022 100GAUI-2 PAM4 53.125
100GAUI-4 NRZ 25.78125
50GAUI-1 PAM4 53.125
50GAUI-2 NRZ 26.5625
IEEE 802.3-2022 25GAUI-1 NRZ 25.78125
IEEE 802.3-2022 200GBASE-KR4/CR4 PAM4 53.125
100GBASE-KR2/CR2 PAM4 53.125
50GBASE-KR/CR PAM4 53.125
IEEE 802.3-2022 100GBASE-KR4 NRZ 25.78125
100GBASE-CR4 NRZ 25.78125
IEEE 802.3-2022 40GBASE-KR4 NRZ 10.3125
40GBASE-CR4 NRZ 10.3125
IEEE 802.3-2022 10GBASE-KR/CR NRZ 10.3125
IEEE 802.3-2022 10GBASE-KX4 NRZ 10.3125
IEEE 802.3-2022 25GBASE-KR/CR NRZ 25.78125
CEI 4.0/5.0 CEI-56G VSR/MR/LR PAM4 36 – 58
CEI-28G VSR/SR/MR NRZ 19.9 – 28.1
IOF-CEI-25G LR NRZ 19.9 – 28.1
CEI-11G SR/MR/LR NRZ 9.95 – 11.2
CEI-6G SR/LR NRZ 4.976 – 6.375
G.709

G.sup56

G.sup43

G.sup58

 OTU0 NRZ 1.327451
OTU1 NRZ 2.666057
OTU1e NRZ 11.049107
OTU2/2e NRZ 10.709225/11.095728
OTU2f NRZ 11.317642
OTU2r NRZ 12.639086
OTU3 NRZ 4x10.754603
OTU4(OTL4.4) NRZ 4x27.952493
OTU4(OTL4.10) NRZ 10x11.180997
G.709.1 100G FlexO-SR (FOIC1.4) NRZ 4x27.952369
100G FlexO-SR (FOIC1.2) PAM4 2x55.904737
100G FlexO-SR (FOIC2.4) PAM4 4x55.904737
100G FlexO-SR (FOIC4.8) PAM4 8x55.904737
G.709, G.709.4 OTU25u NRZ 25.781651
OTU25 NRZ 27.952.493
OTU50u (OTU50u.2-RS) NRZ 2x26.562.914
OTU50u (OTU50u.1-RS) PAM4 53.125827
OTU50 (OTU50.2-RS) NRZ 2x27.952493
OTU50 PAM4 55.904987
PCIE BASE 4.0 PCIE NRZ 2.5, 5, 8, 16
SMPTE 259M SDI NRZ 0.27
SMPTE 292M NRZ 1.485/1.483516484
SMPTE 372M NRZ 2.97/2.967032967
SMPTE ST 2081 NRZ 5.94/5.934065934
SMPTE ST 2082 NRZ 11.88/11.868131868
CPRI V7.0 CPRI NRZ 1.2288
NRZ 2.4576
NRZ 3.072
NRZ 4.9152
NRZ 6.144
NRZ 8.11008
NRZ 9.8304
NRZ 10.1376
NRZ 12.16512
NRZ 24.33024
JESD204B JESD204B NRZ up to 19.2
JESD204C JESD204C NRZ up to 32.45
DP 2.0 DisplayPort 2.0 NRZ 1.62
NRZ 2.7
NRZ 5.4
NRZ 8.1
NRZ 10
NRZ 13.5
NRZ 20
FC-PI-2 Fiber Channel NRZ 1.0625
NRZ 2.125
FC-PI-5 NRZ 4.25
NRZ 8.5
10GFC NRZ 10.52
FC-PI-5 NRZ 14.025
FC-PI-6 NRZ 28.05
FC-PI-7 PAM4 57.8
Serial ATA revision 3.0 Sata Gen 1, 2, 3 NRZ 1, 3, 6
T10/BSR INCITS 519 SAS 1, 2, 3, 4 NRZ 3, 6, 12, 22.5
IEEE 802.3-2022 10G-EPON NRZ 10
IEEE 802.3-2022 1G-EPON NRZ 1
G.984 GPON NRZ 1.25, 2.5, 10.3
CEI-6G-SR Interlaken NRZ 6.25
CEI-11G-SR NRZ 10.3125
CEI-11G-SR+ NRZ 12.5
OIF-28G MR (OIF-CEI3.0) NRZ 25.78125
OIF-CEI 56G PAM4-MR PAM4 53.125
— SerialLite IV NRZ 32
HDMI1.0-1.2a HDMI NRZ 1.65 × 3 = 4.95
HDMI1.3-1.4b NRZ 3.4 × 3 = 10.2
HDMI2.0-2.0b NRZ 6 × 3 = 18
HDMI2.1 NRZ 12 × 4 = 48
SFF8431 SFP+ NRZ 9.8304 – 12.5
ITU-T G.8261 and G.8262 SyncE NRZ/PAM4 10, 25, 50
InfiniBand™ Architecture Specification InfiniBand NRZ 5, 10, 14.062, 25.78125
RapidIO™ Interconnect Specification SRIO NRZ 1.25, 2.5, 3.125, 6.25, 10.3125
109 For protocols which require FGT PAM4 usage, in order to ensure BER compliance please contact Altera Customer Support and reference case 14023487435.
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