Visible to Intel only — GUID: ksk1657772195784
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: ksk1657772195784
Ixiasoft
R-Tile Receiver Specifications
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O standards | PCIe* | High-Speed Differential I/O | — | ||
CXL | High-Speed Differential I/O | — | |||
Peak-to-peak differential input voltage VID (diff p-p) | PCIe* 2.5 GT/s89 | 175 | — | 1,200 | mVPP |
PCIe* 5.0 GT/s89 | 100 | — | 1,200 | mVPP | |
PCIe* 8.0 GT/s89 | 25 | — | 1,200 | mVPP | |
PCIe* 16.0 GT/s89 | 15 | — | 800 | mVPP | |
PCIe* 32.0 GT/s89 | 15 | — | 800 | mVPP | |
CXL 8.0 GT/s89 | 25 | — | 1,200 | mVPP | |
CXL 16.0 GT/s89 | 15 | — | 800 | mVPP | |
CXL 32.0 GT/s89 | 15 | — | 800 | mVPP | |
Differential on-chip termination resistors | PCIe* 90 | 80 | 85 | 120 | Ω |
CXL90 | 80 | 85 | 120 | Ω | |
RCOMP | PCIe* 91 | 148.5 | 150 | 151.5 | Ω |
CXL91 | 148.5 | 150 | 151.5 | Ω |
89 For PCIe* at 2.5 GT/s and 5 GT/s, VID is measured at TP2, which is the accessible test point at the device under test. For PCIe* and CXL 8.0 GT/s, 16.0 GT/s and 32.0 GT/s, VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
90 85ohms (Typical) aligned to Base spec.
91 Connecting RCOMP at 150 Ω calibrates PCIe* and CXL channel on-chip termination to 85 Ω (aligned to Base spec).