Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/15/2024
Public
Document Table of Contents

NOC Reference Clock Requirements

Table 46.  NOC PLL Input Requirements

The specifications in the below table are applicable to the NoC PLL. Supply the referece clock to this NoC PLL which generates the required clock for the Hard Memory NoC.

Connect 1.8 V single-ended clock to the NoC PLL input pins. The valid input refrence clock frequencies are 25 MHz, 100 MHz or 125 MHz only.

The NOC PLL receives its clock signals from the NOC PLL pins. Once you set the PLL frequency during configuration mode, NOC PLL only runs with one specified frequency during user mode. Refer to the related information for information about assigning this pin.

For specification status, see the Data Sheet Status table

Description Min Typ Max Unit
Clock input range 25/100/125 MHz
Clock input accuracy 50 ppm
Clock input duty cycle 45 50 55 %
Clock input peak-to-peak period jitter tolerance 2 %