Visible to Intel only — GUID: ofz1657772107763
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: ofz1657772107763
Ixiasoft
GPIO-B Internal Weak Pull-Up Resistor
All I/O pins in GPIO bank have an option to enable weak pull-up when using 1.05 V, 1.1 V, 1.2 V, and 1.3 V LVCMOS I/O standards.
Symbol | Description | Condition (V) | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
RPU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | VCCIO_PIO = 1.3 ±3% | 3 | 10 | 30 | kΩ |
VCCIO_PIO = 1.2 ±5% | 3 | 10 | 30 | kΩ | ||
VCCIO_PIO = 1.1 ±5% | 3 | 10 | 30 | kΩ | ||
VCCIO_PIO = 1.05 ±5% | 3 | 10 | 30 | kΩ |