Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/15/2024
Public
Document Table of Contents

GPIO-B Differential I/O Standards Specifications

Table 29.  GPIO-B Differential I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VID (mV) VICM(DC) (V) VOD (mV)48 49 VOCM (V)48
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
True Differential Signaling-1.3V (Transmitter & Receiver)50 1.261 1.3 1.339 100 454 0.5 1.37551 247 454 0.9 1 1.1
True Differential Signaling-1.2V (Receiver only)50 1.14 1.2 1.26 100 454 0.8 0.95
True Differential Signaling-1.1V (Receiver only)50 1.045 1.1 1.155 100 454 0.8 0.95
True Differential Signaling-1.05V (Receiver only)50 0.9975 1.05 1.1025 100 454 0.8 0.95
SLVS400 1.164 1.2 1.236 70 0.07 0.2 0.33 140 200 270 0.15 0.2 0.25
1.067 1.1 1.133
48 RL range: 90 ≤ RL ≤ 110 Ω.
49 The specification is only applicable to default VOD and pre-emphasis setting.
50 The True Differential Signaling input buffer is supported on 1.05 V, 1.1 V, 1.2 V, and 1.3 V VCCIO_PIO bank. The maximum input voltage driven into the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.
51 The VICM(DC) voltage must not exceed 1.2 V when on-chip differential termination (RD OCT) is disabled with the use of external on-board termination.