Visible to Intel only — GUID: bcr1657772278038
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: bcr1657772278038
Ixiasoft
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | TX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | TX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | TX_CLK clock period | — | 400 | — | ns |
Tdutycycle (1000Base-T) | TX_CLK duty cycle | 45 | 50 | 55 | % |
Tdutycycle (10/100Base-T) | TX_CLK duty cycle | 40 | 50 | 60 | % |
Td 116 117 | TXD/TX_CTL to TX_CLK output skew | –0.5 | — | 0.5 | ns |
Figure 11. RGMII TX Timing Diagram
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | RX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | RX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | RX_CLK clock period | — | 400 | — | ns |
Tdutycycle (1000Base-T) | RX_CLK duty cycle | 45 | 50 | 55 | % |
Tdutycycle (10/100Base-T) | RX_CLK duty cycle | 40 | 50 | 60 | % |
Tsu | RX_D/RX_CTL to RX_CLK setup time | 1 | — | — | ns |
Th 118 | RX_CLK to RX_D/RX_CTL hold time | 1 | — | — | ns |
Figure 12. RGMII RX Timing Diagram
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | REF_CLK clock period, sourced by HPS TX_CLK | — | 20 | — | ns |
REF_CLK clock period, sourced by external clock source | — | 20 | — | ns | |
Tdutycycle_int | Clock duty cycle, REF_CLK sourced by TX_CLK | 35 | 50 | 65 | % |
Tdutycycle_ext | Clock duty cycle, REF_CLK sourced by external clock source | 35 | 50 | 65 | % |
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Td | TX_CLK to TXD/TX_CTL output data delay | 2 | — | 10 | ns |
Figure 13. RMII TX Timing Diagram
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tsu | RX_D/RX_CTL setup time | 2 | — | — | ns |
Th | RX_D/RX_CTL hold time | 1 | — | — | ns |
Figure 14. RMII RX Timing Diagram
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | MDC clock period | 400 | — | — | ns |
Td | MDC to MDIO output data delay | 10 | — | 300 | ns |
Tsu | Setup time for MDIO data | 10 | — | — | ns |
Th | Hold time for MDIO data | 0 | — | — | ns |
Figure 15. MDIO Timing Diagram
116 Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
117 If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.
118 If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5 – 2 ns, using the HPS I/O programmable delay.