Visible to Intel only — GUID: gjz1657772104091
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: gjz1657772104091
Ixiasoft
GPIO-B OCT Without Calibration Resistance Tolerance Specifications
Symbol | Description | Condition (V) | Calibration Accuracy | Unit |
---|---|---|---|---|
34-Ω and 40-Ω RS | Internal series termination without calibration (34-Ω and 40-Ω setting) | LVCMOS13 I/O standard | 30 | % |
34-Ω and 40-Ω RS 34 | Internal series termination without calibration (34-Ω and 40-Ω setting) | LVCMOS12, SSTL-12, HSTL-12, HSUL-12, and POD12 I/O standards | 25 | % |
34-Ω and 40-Ω RS 34 | Internal series termination without calibration (34-Ω and 40-Ω setting) | LVCMOS11, POD11, and LVSTL11 I/O standards | 25 | % |
34-Ω and 40-Ω RS 34 | Internal series termination without calibration (34-Ω and 40-Ω setting) | LVCMOS105 and LVSTL105 I/O standards | 25 | % |
50-Ω RT 34 | Internal parallel termination without calibration (50-Ω setting) | SSTL-12 and HSTL-12 I/O standards | 25 | % |
POD11 and POD12 I/O standards | 25 | % | ||
LVSTL11 and LVSTL105 I/O standards | 25 | % | ||
100-Ω RD 35 | Internal differential termination (100-Ω setting) | True differential signaling I/O standard at VCCIO_PIO = 1.05 | 40 | % |
True differential signaling I/O standard at VCCIO_PIO = 1.1 | 40 | % | ||
True differential signaling I/O standard at VCCIO_PIO = 1.2 | 40 | % | ||
True differential signaling I/O standard at VCCIO_PIO = 1.3 | 40 | % |
34 This specification applies to both single-ended and pseudo-differential I/O buffers.
35 This specification applies to VICM(DC) ≤ 1.3V. For VICM(DC) > 1.3V, a specification range of -60% to +40% applies.