Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/15/2024
Public
Document Table of Contents

GPIO-B OCT Without Calibration Resistance Tolerance Specifications

Table 15.  GPIO-B OCT Without Calibration Resistance Tolerance Specifications

This table lists the GPIO OCT without calibration resistance tolerance to PVT changes.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Calibration Accuracy Unit
34-Ω and 40-Ω RS Internal series termination without calibration (34-Ω and 40-Ω setting) LVCMOS13 I/O standard 30 %
34-Ω and 40-Ω RS 34 Internal series termination without calibration (34-Ω and 40-Ω setting) LVCMOS12, SSTL-12, HSTL-12, HSUL-12, and POD12 I/O standards 25 %
34-Ω and 40-Ω RS 34 Internal series termination without calibration (34-Ω and 40-Ω setting) LVCMOS11, POD11, and LVSTL11 I/O standards 25 %
34-Ω and 40-Ω RS 34 Internal series termination without calibration (34-Ω and 40-Ω setting) LVCMOS105 and LVSTL105 I/O standards 25 %
50-Ω RT 34 Internal parallel termination without calibration (50-Ω setting) SSTL-12 and HSTL-12 I/O standards 25 %
POD11 and POD12 I/O standards 25 %
LVSTL11 and LVSTL105 I/O standards 25 %
100-Ω RD 35 Internal differential termination (100-Ω setting) True differential signaling I/O standard at VCCIO_PIO = 1.05 40 %
True differential signaling I/O standard at VCCIO_PIO = 1.1 40 %
True differential signaling I/O standard at VCCIO_PIO = 1.2 40 %
True differential signaling I/O standard at VCCIO_PIO = 1.3 40 %
34 This specification applies to both single-ended and pseudo-differential I/O buffers.
35 This specification applies to VICM(DC) ≤ 1.3V. For VICM(DC) > 1.3V, a specification range of -60% to +40% applies.