Visible to Intel only — GUID: byr1657772245488
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: byr1657772245488
Ixiasoft
HPS SD/MMC Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tsdmmc_cclk | SDMMC_CCLK clock period (Identification mode) | 2,500 | — | — | ns |
SDMMC_CCLK clock period (SDR12) | 40 | — | — | ns | |
SDMMC_CCLK clock period (SDR25) | 20 | — | — | ns | |
Tdutycycle | SDMMC_CCLK duty cycle | 45 | 50 | 55 | % |
Tsdmmc_cclk_jitter | SDMMC_CCLK output jitter | — | — | 2 | % |
Tsdmmc_clk | Internal reference clock before division by 4 | 5 | — | — | ns |
Td | SDMMC_CMD/SDMMC_DATA[7:0] output delay114 | –0.5 + Tsdmmc_clk × drvsel/2 | — | 2.5 + (Tsdmmc_clk × drvsel/2) | ns |
Tsu | SDMMC_CMD/SDMMC_DATA[7:0] input setup115 | 6 – (Tsdmmc_clk × smplsel/2) | — | — | ns |
Th | SDMMC_CMD/SDMMC_DATA[7:0] input hold115 | 0.5 + (Tsdmmc_clk × smplsel/2) | — | — | ns |
None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.
Note: SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC interface.
Figure 9. SD/MMC Timing Diagram
114 When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the output delay time is 7.5 to 10.5 ns.
115 When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (sdmmc_clk) is 200 MHz for example, the setup time is 1 ns and the hold time is 5.5 ns.