Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/15/2024
Public
Document Table of Contents

LVDS SERDES Specifications

Table 40.  LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8.

DDR registers support SERDES factor J = 1 to 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table

Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max
Clock frequency fHSCLK_in (input clock frequency) True Differential Signaling I/O Standards Clock boost factor W = 1 to 4071 10 800 10 700 10 625 MHz
fHSCLK_in (input clock frequency) SLVS400 I/O Standards Clock boost factor W = 1 to 4071 10 435.5 10 435.5 10 435.5 MHz
fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor W = 1 to 4071 10 625 10 625 10 525 MHz
fHSCLK_OUT (output clock frequency) 800 700 625 MHz
Transmitter True Differential Signaling I/O Standards - fHSDR (data rate)72 SERDES factor J = 4 and 873 74 75 600 1,600 600 1,600 600 1,250 Mbps
SERDES factor J = 2, uses DDR registers 150 84076 150 76 150 76 Mbps
SERDES factor J = 1, uses DDR registers 150 42076 150 76 150 76 Mbps
tx Jitter - True Differential Signaling I/O Standards Total jitter for data rate, 600 Mbps – 1.6 Gbps ≤1,600 Mbps: 160

≤1,434 Mbps: 200

≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

≤1,600 Mbps: 160

≤1,434 Mbps: 200

≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

ps
tDUTY 77 TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 45 50 55 %
tRISE & tFALL 75 78 True Differential I/O Standards 160 180 200 ps
TCCS 72 77 True Differential I/O Standards 330 330 330 ps
Receiver79 True Differential Signaling I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 and 873 74 75 600 160080 600 160080 600 125080 Mbps
SLVS400 I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 and 873 74 75 600 871 600 871 600 871 Mbps
fHSDR (data rate) (without DPA)72 SERDES factor J = 4 and 873 74 75 75 81 75 81 75 81 Mbps
SERDES factor J = 2, uses DDR registers 75 76 75 76 75 76 Mbps
SERDES factor J = 1, uses DDR registers 75 76 75 76 75 76 Mbps
DPA (FIFO mode) DPA run length ≤10,000 ≤10,000 ≤10,000 UI
DPA (soft CDR mode) DPA run length SGMII/GbE protocol 5 5 5 UI
All other protocols 50 data transition per 208 UI 50 data transition per 208 UI 50 data transition per 208 UI
Soft CDR mode Soft-CDR ppm tolerance –300 300 –300 300 –300 300 ppm
Non DPA mode Sampling window 330 330 330 ps
71 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
72 Requires package skew compensation with PCB trace length.
73 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
74 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
75 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
76 The maximum ideal data rate is the SERDES factor (J) × the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements.
77 Not applicable for DIVCLK = 1.
78 This applies to default pre-emphasis and VOD settings only.
79 You must enable the receiver equalization calibration feature of the input buffer when operating in DPA mode.
80 1.05 V, 1.1 V, and 1.2 V True Differential Signaling I/O standards on receiver supports data rate up to 800 Mbps.
81 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.