Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/15/2024
Public
Document Table of Contents

HPS Power Supply Operating Conditions

Table 12.  HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with ARM-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Typical Maximum Unit
VCCL_HPS HPS core voltage and periphery circuitry power supply Performance boost, fixed voltage: –1V (Typical) – 3% 0.95 (Typical) + 3% V
SmartVID: –1V, –2V, –3V, –3E 32 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCPLLDIG_HPS HPS PLL digital power supply (can be connected to VCCL_HPS) Performance boost, fixed voltage: –1V (Typical) – 3% 0.95 (Typical) + 3% V
SmartVID: –1V, –2V, –3V, –3E 32 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCPLL_HPS HPS PLL analog power supply 1.8 V 1.71 1.8 1.89 V
VCCIO_HPS HPS I/O buffers power supply 1.8 V 1.71 1.8 1.89 V
32 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.