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GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
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AS Configuration Timing
Symbol | Description | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
Tclk 135 | AS_CLK clock period | — | 6.02 | — | ns |
Tdutycycle | AS_CLK duty cycle | 45 | 50 | 55 | % |
Tdcsfrs | AS_nCSO[3:0] asserted to first AS_CLK edge | 8.5136 | — | — | ns |
Tdcslst | Last AS_CLK edge to AS_nCSO[3:0] deasserted | 6.8136 | — | — | ns |
Tdo 137 | AS_DATA[3:0] output delay | –0.6 | — | 0.6 | ns |
Text_delay 138 139 | Total external propagation delay on AS signals | 0 | — | 13.5 | ns |
Tdcsb2b | Minimum delay of slave select deassertion between two back-to-back transfers | 62 | — | — | ns |
Figure 28. AS Configuration Serial Output Timing Diagram
Figure 29. AS Configuration Serial Input Timing Diagram
Related Information
135 AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash setup/hold time specifications and AS timing specifications in this data sheet. For AS using multiple serial flash devices, refer to the related information for the recommended AS_CLK frequency and maximum board loading.
136 AS operating at maximum clock frequency = 166 MHz. The delay is larger when operating at AS clock frequency lower than 166 MHz.
137 Load capacitance for DCLK = 12 pF and AS_DATA = 27 pF. Intel recommends obtaining the Tdo for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash setup time,
- Tsu = Tclk/2 - Tdo(max) + Tbd_clk – Tbd_data(max)
- Tho = Tclk/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
138 Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
- Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
- Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.
- Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
- Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
139 Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency. For more details, refer to the related information.