Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 7/15/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

F-Tile Transmitter Specifications

Table 59.  F-Tile FHT Transmitter Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Min Typical Max Unit
Output eye specifications VTX-DIFF-PKPK Transmit amplitude (low frequency) 800 — 1,200 mVdiff-pkpk
VTX-DEEMP_STEP Transmit tap resolution for c(0), c(1), and c(–1) 0.5 — 5 %
Transmit tap resolution for c(–2) 0.5 — 2.5 %
TTX-SLEW Rise/fall time 8 — — ps
Transmitter output voltage VTX-CM OUT Transmitter output common-mode voltage 820 850 880 mV
Transmitter DC impedance ZTX-DIFF-DC Transmitter output differential DC impedance 100 W mode while configured 80 100 120 Ω
ZTX-CM-DC Transmitter output common-mode DC impedance 20 25 30 Ω
Transmitter return loss ZRL-DIFF-DC Transmitter differential DC return loss — — 14.5 dB
ZRL-DIFF-NYQ Transmitter differential return loss at Nyquist frequency (FBAUD/2) — — 8 dB
ZRL-CMN Transmitter common-mode return loss below 10 GHz — — 6 dB
Electrical idle VTX-IDLE Idle output voltage — — 50 mVpkpk
VCM-DELTA-SQUELCH Maximum common-mode step entering/exiting squelch mode — — 100 mV
TTX-IDLE-LATENCY Latency entering/exiting idle (cold boot) — — 28 ms
Power state cycle (re-establish CM) — — 5 µs
Table 60.  F-Tile FGT Transmitter Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Min Typical Max Unit
Output eye specifications VTX-DIFF-PKPK Back-porch transmit amplitude 300  — 1,050 mV
VTX-DEEMP_STEP Transmit tap resolution — — 2 %
DTX-N+2-DEEMP N+2 precursor tap de-emphasis 0 — 2.5 dB
DTX-N+1-DEEMP N+1 precursor tap de-emphasis 0 — 4.5 dB
DTX-N-1-DEEMP N-1 postcursor tap de-emphasis 0 — 6.5 dB
TTX-SLEW Rise/fall time at 20%–80% 10 — 20 ps
TTX-DJ Transmit deterministic jitter at 25 Gbps — — 0.15 UIpkpk
TTX-RJ Transmit total peak-peak random jitter (assumes 14σTXRJ-RMS)99 — — 0.15 UIpkpk
TTX-TJ Transmit total peak-peak jitter (TTX-TJ = TTX-DDJ + TTX-PJ + TTX-RJ)99 — — 0.28 UIpkpk
Transmitter output voltage VTX-CM OUT Transmitter output common-mode voltage 0.45 0.5 0.55 V
Transmitter DC impedance ZTX-DIFF-DC Transmitter output differential DC impedance 90 Ω mode while configured100 80 90 120 Ω
ZTX-CM-DC Transmitter output common-mode DC impedance 20 25 30 Ω
Transmitter return loss ZRL-DIFF-DC Transmitter differential DC return loss — — 12 dB
ZRL-DIFF-NYQ Transmitter differential return loss at Nyquist frequency (FBAUD/2) — — 6 dB
ZRL-CMN Transmitter common-mode return loss below 10 GHz — — 6 dB
Electrical idle VTX-IDLE Idle output voltage — — 20 mV
VCM-DELTA-SQUELCH Maximum common-mode step entering/exiting squelch mode — — 100 mV
TTX-IDLE-LATENCY Latency entering/exiting idle (cold boot), power state cycle (re-establish CM) — — 8 µs
Receiver detect VTX-RCV-DETECT Voltage change allowed during receiver detection — — 600 mV
Lane-to-lane output skew — Lane count ≤ 8 — — 2 UI + 200 ps ps
— Lane count = 16 — — 2 UI + 300 ps ps
99 Assume a 1st order high-pass jitter measurement filter with a cutoff of Fbaud/Fgpll = Ngpll.
100 TX pins are driven to 0 V before mode configuration.
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