Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

HPS I2C Timing Characteristics

Table 80.  HPS I2C Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 — 2.5 — μs
Tclk_jitter I2C clock output jitter — 2 — 2 %
THIGH 120 SCL high period 4121 — 0.6122 — μs
TLOW 123 SCL low period 4.7124 — 1.3125 — μs
TSU;DAT Setup time for serial data line (SDA) data to SCL 0.25 — 0.1 — μs
THD;DAT 126 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
TVD;DAT and TVD;ACK 127 SCL to SDA output data delay — 3.45128 — 0.9129 μs
TSU;STA Setup time for a repeated start condition 4.7 — 0.6 — μs
THD;STA Hold time for a repeated start condition 4 — 0.6 — μs
TSU;STO Setup time for a stop condition 4 — 0.6 — μs
TBUF SDA high pulse duration between STOP and START 4.7 — 1.3 — μs
Tscl:r 130 SCL rise time — 1,000 20 300 ns
Tscl:f 130 SCL fall time — 300 6.54 300 ns
Tsda:r 130 SDA rise time — 1,000 20 300 ns
Tsda:f 130 SDA fall time — 300 6.54 300 ns
Figure 16. I2C Timing Diagram
Related Information
120 You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
121 The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the related information for the SCL_High_time equation.
122 The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the related information for the SCL_High_time equation.
123 You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
124 The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the related information for the SCL_Low_time equation.
125 The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the related information for the SCL_Low_time equation.
126 THD;DAT is affected by the rise and fall time.
127 TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
128 Use maximum SDA_HOLD = 240 to be within the specification.
129 Use maximum SDA_HOLD = 60 to be within the specification.
130 Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value, and total capacitance on the transmission line.
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