Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 7/15/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

I/O PLL Specifications

Table 32.  I/O PLL Specifications

The specifications in this table are applicable to I/O bank I/O PLL , fabric-feeding I/O PLL, and UIB fabric-feeding PLL.

For specification status, see the Data Sheet Status table

Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency source from Core Clock Input or Reference Clock Input –1V 10 — 1,10053 MHz
–2V 10 — 1,00053 MHz
–3V, –3E 10 — 78053 MHz
Input clock frequency source from IO Clock Input –1V 10 — 80053 MHz
–2V 10 — 71753 MHz
–3V, –3E 10 — 62553 MHz
fINPFD Input clock frequency to the PFD — 10 — 325 MHz
fVCO I/O PLL VCO operating range –1V 600 — 3,200 MHz
–2V 600 — 3,200 MHz
–3V, –3E 600 — 2,400 MHz
fCLBW I/O PLL closed-loop bandwidth — 0.5 — 20 MHz
fOUT Output frequency for internal clock (C counter) –1V — — 1,100 MHz
–2V — — 1,000 MHz
–3V, –3E — — 780 MHz
fOUT_EXT Output frequency for external clock output –1V — — 800 MHz
–2V — — 717 MHz
–3V, –3E — — 625 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) fOUT_EXT < 300 MHz 45 50 55 %
fOUT_EXT ≥ 300 MHz 40/45 54 50 55 54/60 %
tFCOMP 55 External feedback clock compensation time — — — 5 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk — — — 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms
tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on the areset signal — 10 — — ns
tINCCJ Input clock cycle-to-cycle jitter fREF < 100 MHz 56 — — ±750 ps (p-p)
fREF ≥ 100 MHz 56 — — 0.15 UI (p-p)
tREFPJ Reference phase jitter (rms)57 Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz — — 1.42 ps
tREFPN Reference phase noise58 57 10 Hz — — –90 dBc/Hz
100 Hz — — –100 dBc/Hz
1 kHz — — –110 dBc/Hz
10 kHz — — –120 dBc/Hz
100 kHz — — –130 dBc/Hz
1 MHz — — –138 dBc/Hz
10 MHz — — –142 dBc/Hz
100 MHz — — –144 dBc/Hz
tOUTPJ_DC 55 59 Period jitter for dedicated clock output fOUT < 100 MHz 56 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 56 — — 175 ps (p-p)
tOUTCCJ_DC 55 59 Cycle-to-cycle jitter for dedicated clock output fOUT < 100 MHz 56 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 56 — — 175 ps (p-p)
tOUTPJ_IO 60 59 Period jitter for clock output on the regular I/O fOUT < 100 MHz 56 — — 60 mUI (p-p)
fOUT ≥ 100 MHz 56 — — 600 ps (p-p)
tOUTCCJ_IO 60 59 Cycle-to-cycle jitter for clock output on the regular I/O fOUT < 100 MHz 56 — — 60 mUI (p-p)
fOUT ≥ 100 MHz 56 — — 600 ps (p-p)
tCASC_OUTPJ_DC 55 Period jitter for dedicated clock output in cascaded PLLs fOUT < 100 MHz 56 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 56 — — 175 ps (p-p)
Related Information
53 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
54 To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to the related information for the detail design guidelines.
55 Not applicable for fabric-feeding PLL.
56 fREF is fIN/N, specification applies when N = 1.
57 Requirement for Advanced Interface Bus (AIB), High Bandwidth Memory (HBM) Interface, DDR/LPDDR protocol, and LVDS SERDES applications only.
58 The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).
59 This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the related information for the recommended spread-spectrum clock profile.
60 External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output Clock Jitter Specifications table.
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