Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/15/2024
Public
Document Table of Contents

GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications

Table 23.  GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) Internal VREF (V) VTT (V)
Min Typ Max Min Typ Max Min Typ Max
SSTL-12 1.14 1.2 1.26 0.49 × VCCIO_PIO 0.5 × VCCIO_PIO 0.51 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
HSTL-12 1.14 1.2 1.26 0.47 × VCCIO_PIO 0.5 × VCCIO_PIO 0.53 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
HSUL-1240 1.14 1.2 1.26 0.49 × VCCIO_PIO 0.5 × VCCIO_PIO 0.51 × VCCIO_PIO 0.45 × VCCIO_PIO 0.5 × VCCIO_PIO 0.55 × VCCIO_PIO
POD1241 1.164 1.2 1.236 0.69 × VCCIO_PIO 0.7 × VCCIO_PIO 0.71 × VCCIO_PIO VCCIO_PIO
POD1141 1.067 1.1 1.133 0.69 × VCCIO_PIO 0.7 × VCCIO_PIO 0.71 × VCCIO_PIO VCCIO_PIO
LVSTL1141 1.067 1.1 1.133 0.075 0.2 0.35 GND
LVSTL10541 1.0185 1.05 1.0815 0.075 0.2 0.35 GND
LVSTL700 1.0185 1.05 1.0815 0.075 0.2 0.35 GND
40 Usage of receiver termination is optional.
41 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
  • PHYLITE mode
  • GPIO mode