Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 7/15/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

Document Revision History for the Intel Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series

Document Version Changes
2023.12.15
  • Added AGM 039 R31B package in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs M-Series table.
  • Updated the CONF_DONE and INIT_DONE signals in the General Configuration Timing Diagram and added a note for the signals.
  • Included specifications for Input Clock Frequency Source from IO Clock Input in I/O PLL Specifications table.
  • Updated Parameter: Input Clock Frequency to Input Clock Frequency Source from Core Clock Input or Reference Clock Input.
  • Updated the Recommended Operating Conditions table.
    • Added IFUSEWR symbol.
    • Updated the extended grade minimum TJ specifications.
    • Added clarity for the industrial grade minimum TJ specifications.
  • Updated the maximum value of V CCFUSEWR_SDM in the Absolute Maximum Ratings table.
  • Updated VCCIO_PIO footnote in the following tables:
    • Recommended Operating Conditions
    • GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
    • GPIO-B Single-Ended LVSTL I/O Standards Specifications
    • GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
    • GPIO-B Differential POD I/O Standards Specifications
    • GPIO-B Differential LVSTL I/O Standards Specifications
  • Added LVSTL11, LVSTL105, and LVSTL700 I/O Standards in GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage table.
  • Removed 1.1 V support for LVSTL700 standard in the Table: GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications and GPIO-B Single-Ended LVSTL I/O Standards Specifications.
  • Updated the VOD maximum specifications for True Differential Signaling -1.3V (Transmitter and Receiver) I/O Standard in GPIO-B Differential I/O Standards Specifications table.
  • Added SLVS-400 support and footnote in LVDS SERDES Specifications table.
  • Updated the ideality factors when using lower injection current (two-currents) in Remote Temperature Diode section.
  • Updated note in Voltage Sensor Specifications section.
  • Updated supported –2 transceiver speed grade data rate for NRZ in the F-Tile FGT Transmitter and Receiver Data Rate Performance.
  • Added footnote in F-Tile FGT Electrical Compliance List table.
  • Removed XSR support in CEI 4.0/5.0 specifications in the F-Tile FHT Electrical Compliance List table.
  • Updated the VRX-DIFF-PKPK specifications F-Tile FGT Receiver Electrical Specifications table.
  • Updated the Programmable IOE Delay section.
    • Removed -I1V, -I2V, and -I3V speed grades.
    • Updated IOE delay in all speed grades.
2023.07.13 Removed the note about restricted support for M-Series FPGAs.
2023.05.05 Initial release.
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