F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

3.3. Simulation

The testbech povides basic fuctioality such as the statup ad wait fo lock ad sed ad eceive a few packets utilizig the PTP featue.
Sice Fast Sim model does ot suppot the PTP timestamp accuacy, the model is ot eabled by default i the desigs with eabled PTP featue. To utilize the Fast Sim model fo fuctioal pupose simulatio, efe to Fast Sim Model fo FGT Vaiats.
Note: I PTP desig examples, the simulatio pitout displays the timestamp accuacy as RX ITS - TX ETS ifomatio.
  1. Asset global eset (i_st_) to eset the F-Tile Etheet Itel FPGA Had IP.
  2. Wait util esets ackowledgmet. The o_st_ack_ sigal goes low.
  3. Deassets the global eset.
  4. Wait util o_tx_laes_stable bit is set to 1, idicatig TX path is eady.
  5. Wait util o_x_pcs_eady bit is set to 1, idicatig RX path is eady.
  6. Pefom the PTP use flow util tx_ptp_eady ad x_ptp_eady sigals ae set to 1.
  7. Wite to PTP Asymmety Delay ad pee-to-pee MeaPathDelay Avalo® memoy-mapped iteface egistes.
  8. Reset the PTP moito.
  9. Read TX packet data ifomatio fom 0x00 - 0x34 egistes i sequetial ode.
    • 0x00: Set hw_pc_ctl[6] = 1'b1 to eable sapshot bit to ead the TX packet statistics.
    • 0x020/0x24: TX stat of packet coute (LSB/MSB)
    • 0x28/0x2C: TX ed of packet coute (LSB/MSB)
    • 0x30/0x34: TX eo coute (LSB/MSB)
    • 0x00: Set hw_pc_ctl[6] = 1'b0 to disable sapshot bit.
  10. Read RX packet data ifomatio fom 0x38 - 0x4C egistes i sequetial ode.
    • 0x00: Set hw_pc_ctl[6] = 1'b1 to eable sapshot bit to ead the RX packet statistics.
    • 0x38/0x3C: RX stat of packet coute (LSB/MSB)
    • 0x40/0x44: RX ed of packet coute (LSB/MSB)
    • 0x48/0x4C: RX eo coute (LSB/MSB)
    • 0x00: Set hw_pc_ctl[6] = 1'b0 to disable sapshot bit.
  11. Compae ead coutes to esue 16 packets wee set ad eceived.
  12. Istuct packet cliet to stop data tasmissio ad clea the coutes by witig hw_pc_ctl[2:0]=3'b100 to stop the packet geeato.
  13. Stat the PTP checke.
    1. Wait util the packet tasmissio is complete. Poll the TX_PKT_VALID bit to moito the tasmissio status.
    2. Read TX packet data ifomatio fom 0x102 - 0x104 egistes i sequetial ode, statig fom the 0x102 egiste. The PTP moito logic efeshes the 0x102 - 0x104 egistes cotet to ext data whe ead fom 0x104 egiste.
    3. Repeat the pevious step util the TX_PKT_EOP bit is set to 1 idicatig the ead opeatio eached the ed of the packet.
    4. Read TX PTP commad ifomatio fom 0x105 - 0x10A egistes i sequetial ode, statig fom the 0x105 egiste. The PTP moito logic efeshes the 0x105 - 0x10A egistes cotet to ext data whe ead fom 0x10A egiste.
    5. If TX PTP commad idicates a PTP packet:
      1. Wait util the TX egess timestamp is available. Use the TX_PTP_ETS_VALID sigal to moito the status.
      2. Read the TX egess timestamp fom the 0x10C - 0x10F egistes i sequetial ode, statig with the 0x10C egiste.
      The PTP moito logic efeshes cotet of 0x10C - 0x10F egistes to ext data whe ead fom the 0x10F egiste.
    6. Wait util the packets ae loop backed i the RX data path. Poll the RX_PKT_VALID bit to moito the tasmissio status.
    7. Read RX packet data ifomatio fom 0x110 - 0x112 egistes i sequetial ode, statig with the 0x110 egiste. The PTP moito logic efeshes the 0x110 - 0x112 egistes cotet to ext data whe ead fom 0x112 egiste.
    8. Repeat the pevious step util the RX_PKT_EOP bit is set to 1 idicatig the ead opeatio eached the ed of the packet.
    9. Read RX igess timestamp.
      1. Read the RX igess timestamp fom the 0x114 - 0x116 egistes i sequetial ode, statig with the 0x14 egiste. The PTP moito logic efeshes the 0x114 - 0x116 egistes cotet to ext data whe ead fom 0x116 egiste.
    10. Display the TX packet cotet, RX packet cotet, TX PTP commads, TX egess timestamp, ad RX igess timestamp ifomatio.
    11. Display the compaiso ifomatio. Note that i 1-step commads, the TX/RX packets ad PTP commads field cotet is the same.
    12. Repeat steps b though step k util the system pocesses all packets.
      Note: The desig example simulatio pefoms step 14 fo oly fist six packets to educe log simulatio time.
  14. Pefom Avalo® memoy-mapped iteface test o PTP-elated egistes.
    • Selective PTP Asymmety Delay ad P2P MeaPathDelay egistes
    • Selective Maste TOD Avalo® memoy-mapped iteface egistes
  15. Pefom Avalo® memoy-mapped iteface test. Wite ad ead Etheet IP egistes.
    • 0x104: Scatch egiste
    • 0x108: Etheet IP soft eset egiste
    • 0x214: TX MAC souce addess egiste [31:0]
    • 0x218: TX MAC souce addess egiste [47:32]
    • 0x21C: RX MAC fame size egiste
  16. Pefom Avalo® memoy-mapped iteface 2 test. Wite ad ead tasceive egistes.

The followig sample output illustates a successful simulatio test: 

203145s : Fame moitoed by basic_avl_tb_top.U_MON_TX
203145s : Fame legth : 128
203145s : Empty : 0
	----------------------------------------------------------
	      |  00 01 02 03 04 05 06 07  08 09 10 11 12 13 14 15 
	----------------------------------------------------------
	 0000 |  ab e4 23 39 f0 00 1e 84  33 9f 01 00 88 f7 00 00 
	 0010 |  10 11 12 13 aa 15 16 aa  18 19 1a 1b 1c 1d 1e 1f 
	 0020 |  20 21 22 23 bb cc 26 27  28 29 2a 2b 2c 2d 2e 2f 
	 0030 |  30 31 32 33 34 35 36 37  bb cc 3a 3b 3c 3d 3e 3f 
	 0040 |  40 41 42 43 44 45 46 47  48 49 4a 4b 4c 4d 4e 4f 
	 0050 |  50 51 52 53 54 55 56 57  58 59 5a 5b 5c 5d 5e 5f 
	 0060 |  60 61 62 63 64 65 66 67  68 69 6a 6b 6c 6d 6e 6f 
	 0070 |  70 71 72 73 74 75 76 77  78 79 7a 7b 7c 7d 7e 7f 
	----------------------------------------------------------

PTP Commad foud.
tx_timestamp_q.push_back
The time ow is 210000s 

210805s : Fame moitoed by basic_avl_tb_top.U_MON_RX
210805s : Fame legth : 128
210805s : Empty : 0
	----------------------------------------------------------
	      |  00 01 02 03 04 05 06 07  08 09 10 11 12 13 14 15 
	----------------------------------------------------------
	 0000 |  ab e4 23 39 f0 00 1e 84  33 9f 01 00 88 f7 00 00 
	 0010 |  10 11 12 13 aa 15 16 aa  18 19 1a 1b 1c 1d 1e 1f 
	 0020 |  20 21 22 23 bb cc 26 27  28 29 2a 2b 2c 2d 2e 2f 
	 0030 |  30 31 32 33 34 35 36 37  bb cc 3a 3b 3c 3d 3e 3f 
	 0040 |  40 41 42 43 44 45 46 47  48 49 4a 4b 4c 4d 4e 4f 
	 0050 |  50 51 52 53 54 55 56 57  58 59 5a 5b 5c 5d 5e 5f 
	 0060 |  60 61 62 63 64 65 66 67  68 69 6a 6b 6c 6d 6e 6f 
	 0070 |  70 71 72 73 74 75 76 77  78 79 7a 7b 7c 7d 7e 7f 
	----------------------------------------------------------

------------------------------
TX PTP Commad #1
------------------------------
Egess Timestamp Request            : 1
Iset Timestamp                    : 0
Update CoectioField              : 0
Clea UDP/IPv4 Checksum             : 0
Update UDP/IPv6 Exteded Bytes      : 0
Add Pee-to-Pee (P2P) MiPathDelay : 0
Add Asymmety Delay                 : 0
Asymmety Delay Sig                : 0
Asymmety & P2P MiPathDelay Select : 0
Timestamp Field Offset              : 0x0000
Coectio Field Offset             : 0x0000
TX Figepit Data                 : 0x00000001
TX Igess Timestamp                : 0x00000000000000001234abcd
------------------------------
Timestamps #1
------------------------------
TX Egess Timestamp                 : 0x000000000000000265ae2c80
RX Igess Timestamp                : 0x000000000000000265ae1680
TX Use Figepit                 : 0x00000001
TX Retued Figepit             : 0x00000001
------------------------------
Compaiso #1
------------------------------
RX_ITS - TX_ETS       : 0x1ffffffffffffffffffffea00/-0.0859 s

TX Timestamp Fields   : 0x3031323334353637bbcc
RX Timestamp Fields   : 0x3031323334353637bbcc

TX Coectio Fields  : 0x16aa18191a1b1c1d
RX Coectio Fields  : 0x16aa18191a1b1c1d
Related Ifomatio
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