F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

6.3. Simulation

The testbech povides basic fuctioality such as the statup ad waits fo lock ad sed ad eceive a few packets usig the ROM-based packet geeato
Impotat: Befoe the simulatio, you must geeate tile-elated files ad specify the colocate assigmet i the .qsf file to map both the istaces of F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IP to the F-Tile Etheet Itel FPGA Had IP fo successful simulatio as show below.
Note:
  1. Apped the eth_f_hw.qsf file as show below:
    • Use the followig sytax to colocate assigmets:
      set_istace_assigmet -ame IP_COLOCATE 
-fom <ANLT IP hieachical path>  -to <Etheet hieachical path> <tile type>
    • Example:
      set_istace_assigmet -ame IP_COLOCATE 
-fom ANLT IP INST0[0].k_dut|eth_alt_f_0 -to IP_INST[0].hw_ip_top|dut|eth_f_0 F_TILE
      set_istace_assigmet -ame IP_COLOCATE 
-fom ANLT_IP_INST1[1].k_dut|eth_alt_f_0 -to IP_INST[0].hw_ip_top|dut|eth_f_0 F_TILE
  2. At the commad pompt, avigate to the hadwae_test_desig folde i you example desig:
    cd <you_desig_path>/hadwae_test_desig
  3. Ru the followig commad to geeate eth_f_hw_tiles files:
    quatus_tlg eth_f_hw
  4. At the commad pompt, chage to the testbech simulatio diectoy.
    CD <desig_example_di>/ex_*G/sim
  5. Ru the IP setup simulatio:
    ip-setup-simulatio --quatus-poject=../../hadwae_test_desig/eth_f_hw.qpf
  6. Add the followig maco to you simulatio u scipt fo AN/LT eabled desigs:
    • Fo FGT
      +defie+INTC_SIM_AN_LT_ENABLE
    • Fo FHT
      +defie+RTL
    Note: I geeated desig example, the colocate assigmets ae aleady available i qsf file by default. Theefoe, steps 1 to 5 ca be skipped i the desig example.
Figue 19.  F-Tile Etheet Itel FPGA Had IP Simulatio Desig Example Block Diagam with Eabled Auto-Negotiatio ad Lik Taiig
The followig steps show the simulatio testbech flow:
  1. Asset global esets (i_st_ ad i_ecofig_st) to eset the F-Tile Etheet Itel FPGA Had IP ad F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IP.
  2. Wait util cofiguatio settigs load.
  3. Wait util esets ackowledgmet. The o_st_ack_ sigal goes low.
  4. Deassets the global esets, i_st_ ad i_ecofig_st.
  5. Wait util auto-egotiatio is complete. The data mode begis.
  6. Wait util lik taiig is complete.
  7. Wait util o_tx_laes_stable bit is set to 1, idicatig TX path is eady.
  8. Wait util o_x_pcs_eady bit is set to 1, idicatig RX path is eady.
  9. Repeat steps 4 ad 5 to complete the eset sequece fo all the IP istaces.
  10. Istuct packet cliet to tasmit data. Wite hw_pc_ctl[0]=1'b1 to stat the packet geeato.
  11. Read TX packet data ifomatio fom 0x20 - 0x34 egistes. Read egiste i sequetial ode.
  12. Read RX packet data ifomatio fom 0x38 - 0x4C egistes. Read egiste i sequetial ode.
  13. Compae the coutes to esue 16 packets wee set ad eceived.
  14. Istuct packet cliet to stop data tasmissio. Wite hw_pc_ctl[2:0]=3'b100 to stop the packet geeato. Clea coutes.
  15. Repeat steps 7 though 11 to simulate packet tasfe fo each of the istatiated IPs.
  16. Pefom Avalo® memoy-mapped iteface test. Wite ad ead Etheet IP egistes.
    • 0x104: Scatch egiste
    • 0x108: IP soft eset egiste
    • 0x214: TX MAX souce addess egiste [31:0]
    • 0x218: TX MAX souce addess egiste [47:32]
    • 0x21C: RX MAX fame size egiste
  17. Pefom Avalo® memoy-mapped iteface 2 test to ead ad wite opeatio tasceive egistes.
  18. Repeat steps 13 ad 14 fo each istatiated IP i a sequetial ode.
The followig sample output illustates a successful simulatio test u. 
---TX eset sequece completed -----
---RX eset sequece completed --------
---Statig Data mode afte completig AN -------IP_INST[  0] Test    0;   ---Total     16 packets to sed-----
------IP_INST[  0] Stat pkt ge TX-----
The time ow is 7020000s 

------Checkig Packet TX/RX esult-----
------------  16 packets Set;     0 packets Received--------
------ --- ALL 6  packets Set out---
------------  16 packets Set;     2 packets Received--------
------------  16 packets Set;    16 packets Received--------
------ ---ALL 16 packets Received---
------TX/RX packet check OK---

---IP_INST[1] Test    0;  
 ---Total 16 packets to sed-----
------IP_INST[1] Stat pkt ge TX-----
------Checkig Packet TX/RX esult-----
------------  16 packets Set;     0 packets Received--------
----------ALL 16  packets Set out---
------------  16 packets Set;  0 packets Received--------
------------  16 packets Set;  16 packets Received--------
----------ALL 16  packets Received---
------TX/RX packet check OK---

****Statig AVMM Read/Wite****
====>MATCH!  Read add = 00000104, ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 

====>MATCH!  Read add = 000001f0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 

====>MATCH!  Read add = 00100004, ReaddataValid = 1 Readdata = c232d284 Expected_Readdata = c232d284 

====>MATCH!  Read add = 00100008, ReaddataValid = 1 Readdata = 53aefda7 Expected_Readdata = 53aefda7 

====>MATCH!  Read add = 00100080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 

====>MATCH!  Read add = 00300080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 

====>MATCH!  Read add = 00000af0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 

====>MATCH!  Read add = 00005214, ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 

====>MATCH!  Read add = 00005218, ReaddataValid = 1 Readdata = 00000011 Expected_Readdata = 00000011 

====>MATCH!  Read add = 0000521c, ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee 

====>MATCH!  Read add = 00005214, ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 

====>MATCH!  Read add = 00005218, ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab 

7026356s  Ty to access AVMM2 begi...
7026356s  Ty to access AVMM2 begi...
7026356s  wite 0x00000065 to xcv  0 addess 0x008f0010
7026958s  Ty to access AVMM2 ed...
7026958s  ead fom addess 0x008f0010
====>MATCH!  Read add = 008f0010, ReaddataValid = 1 Readdata = 00000065 Expected_Readdata = 00000065 

7027539s  Ty to access AVMM2 ed...
7027540s  Ty to access AVMM2 begi...
7027540s  wite 0x00000066 to xcv  1 addess 0x009f0011
7028141s  Ty to access AVMM2 ed...
7028142s  ead fom addess 0x009f0011
====>MATCH!  Read add = 009f0011, ReaddataValid = 1 Readdata = 00000066 Expected_Readdata = 00000066 

7028723s  Ty to access AVMM2 ed...
7028724s  Ty to access AVMM2 begi...
7028724s  wite 0x00000067 to xcv  2 addess 0x00af0012
7029325s  Ty to access AVMM2 ed...
7029326s  ead fom addess 0x00af0012
====>MATCH!  Read add = 00af0012, ReaddataValid = 1 Readdata = 00000067 Expected_Readdata = 00000067 

7029907s  Ty to access AVMM2 ed...
7029908s  Ty to access AVMM2 begi...
7029908s  wite 0x00000068 to xcv  3 addess 0x00bf0013
The time ow is 7030000s 

7030509s  Ty to access AVMM2 ed...
7030510s  ead fom addess 0x00bf0013
====>MATCH!  Read add = 00bf0013, ReaddataValid = 1 Readdata = 00000068 Expected_Readdata = 00000068 

7031091s  Ty to access AVMM2 ed...
7031092s  Ty to access AVMM2 begi...
7031092s  wite 0x00000069 to xcv  4 addess 0x00cf0014
7031693s  Ty to access AVMM2 ed...
7031694s  ead fom addess 0x00cf0014
====>MATCH!  Read add = 00cf0014, ReaddataValid = 1 Readdata = 00000069 Expected_Readdata = 00000069 

7032274s  Ty to access AVMM2 ed...
7032275s  Ty to access AVMM2 begi...
7032275s  wite 0x0000006a to xcv  5 addess 0x00df0015
7032876s  Ty to access AVMM2 ed...
7032877s  ead fom addess 0x00df0015
====>MATCH!  Read add = 00df0015, ReaddataValid = 1 Readdata = 0000006a Expected_Readdata = 0000006a 

7033458s  Ty to access AVMM2 ed...
7033459s  Ty to access AVMM2 begi...
7033459s  wite 0x0000006b to xcv  6 addess 0x00ef0016
7034060s  Ty to access AVMM2 ed...
7034061s  ead fom addess 0x00ef0016
====>MATCH!  Read add = 00ef0016, ReaddataValid = 1 Readdata = 0000006b Expected_Readdata = 0000006b 

7034642s  Ty to access AVMM2 ed...
7034643s  Ty to access AVMM2 begi...
7034643s  wite 0x0000006c to xcv  7 addess 0x00ff0017
7035244s  Ty to access AVMM2 ed...
7035245s  ead fom addess 0x00ff0017
====>MATCH!  Read add = 00ff0017, ReaddataValid = 1 Readdata = 0000006c Expected_Readdata = 0000006c 

7035826s  Ty to access AVMM2 ed...
**** AVMM Read/Wite Opeatio Completed fo IP_INST[  0]****
****Statig AVMM Read/Wite****
====>MATCH!  Read add = 01000104, ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 

====>MATCH!  Read add = 010001f0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 

====>MATCH!  Read add = 01100004, ReaddataValid = 1 Readdata = b50c786a Expected_Readdata = b50c786a 

====>MATCH!  Read add = 01100008, ReaddataValid = 1 Readdata = d6bee8ad Expected_Readdata = d6bee8ad 

====>MATCH!  Read add = 01100080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 

====>MATCH!  Read add = 01300080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 

====>MATCH!  Read add = 01000af0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 

====>MATCH!  Read add = 01005214, ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 

====>MATCH!  Read add = 01005218, ReaddataValid = 1 Readdata = 00000011 Expected_Readdata = 00000011 

====>MATCH!  Read add = 0100521c, ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee 

The time ow is 7040000s 

====>MATCH!  Read add = 01005214, ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 

====>MATCH!  Read add = 01005218, ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab 

7040852s  Ty to access AVMM2 begi...
7040852s  Ty to access AVMM2 begi...
7040852s  wite 0x00000065 to xcv  0 addess 0x018f0010
7041454s  Ty to access AVMM2 ed...
7041454s  ead fom addess 0x018f0010
====>MATCH!  Read add = 018f0010, ReaddataValid = 1 Readdata = 00000065 Expected_Readdata = 00000065 

7042035s  Ty to access AVMM2 ed...
7042036s  Ty to access AVMM2 begi...
7042036s  wite 0x00000066 to xcv  1 addess 0x019f0011
7042637s  Ty to access AVMM2 ed...
7042638s  ead fom addess 0x019f0011
====>MATCH!  Read add = 019f0011, ReaddataValid = 1 Readdata = 00000066 Expected_Readdata = 00000066 

7043219s  Ty to access AVMM2 ed...
7043220s  Ty to access AVMM2 begi...
7043220s  wite 0x00000067 to xcv  2 addess 0x01af0012
7043821s  Ty to access AVMM2 ed...
7043822s  ead fom addess 0x01af0012
====>MATCH!  Read add = 01af0012, ReaddataValid = 1 Readdata = 00000067 Expected_Readdata = 00000067 

7044403s  Ty to access AVMM2 ed...
7044404s  Ty to access AVMM2 begi...
7044404s  wite 0x00000068 to xcv  3 addess 0x01bf0013
7045005s  Ty to access AVMM2 ed...
7045006s  ead fom addess 0x01bf0013
====>MATCH!  Read add = 01bf0013, ReaddataValid = 1 Readdata = 00000068 Expected_Readdata = 00000068 

7045587s  Ty to access AVMM2 ed...
7045588s  Ty to access AVMM2 begi...
7045588s  wite 0x00000069 to xcv  4 addess 0x01cf0014
7046189s  Ty to access AVMM2 ed...
7046190s  ead fom addess 0x01cf0014
====>MATCH!  Read add = 01cf0014, ReaddataValid = 1 Readdata = 00000069 Expected_Readdata = 00000069 

7046770s  Ty to access AVMM2 ed...
7046771s  Ty to access AVMM2 begi...
7046771s  wite 0x0000006a to xcv  5 addess 0x01df0015
7047372s  Ty to access AVMM2 ed...
7047373s  ead fom addess 0x01df0015
====>MATCH!  Read add = 01df0015, ReaddataValid = 1 Readdata = 0000006a Expected_Readdata = 0000006a 

7047954s  Ty to access AVMM2 ed...
7047955s  Ty to access AVMM2 begi...
7047955s  wite 0x0000006b to xcv  6 addess 0x01ef0016
7048556s  Ty to access AVMM2 ed...
7048557s  ead fom addess 0x01ef0016
====>MATCH!  Read add = 01ef0016, ReaddataValid = 1 Readdata = 0000006b Expected_Readdata = 0000006b 

7049138s  Ty to access AVMM2 ed...
7049139s  Ty to access AVMM2 begi...
7049139s  wite 0x0000006c to xcv  7 addess 0x01ff0017
7049740s  Ty to access AVMM2 ed...
7049741s  ead fom addess 0x01ff0017
The time ow is 7050000s 

====>MATCH!  Read add = 01ff0017, ReaddataValid = 1 Readdata = 0000006c Expected_Readdata = 0000006c 

7050322s  Ty to access AVMM2 ed...
**** AVMM Read/Wite Opeatio Completed fo IP_INST[  1]****
** Testbech complete
**
Note: The simulatio completio may take a loge time. To cofim the simulatio is pogessig successfully, veify the itemediate outputs fom the System Cosole such as bigig the base ad AN/LT IP out of esets, IP esettig sequece, Auto-egotiatio ad lik taiig auto-coectio completio, ad othes.
Level Two Title