F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.3.1. Fast Sim Model for FGT Variants

To povide a eductio i a eal-time simulatio duatio, you ca utilize a Fast Sim model i you desig example testbech. Fo FGT vaiats, the model is eabled by a maco i the simulatio u scipt.
To eable the Fast Sim model, add the followig maco to you simulatio u scipt: 
+defie+IP7581SERDES_UX_SIMSPEED
The desig example simulatio scipt eables the maco by default fo all FGT vaiats with the exceptio of vaiat auto-egotiatio ad lik taiig.
  • I PTP vaiats, a additioal switch must be defied a show below.
    +defie+UX_WORD_CLK_DRIFT_CORRECTION
    This switch eables the coectios fo timestamp accuacy issues i the FGT fast sim model.
    Note: The FGT Fast Sim Model with PTP eabled ca suppot up to 10,000 μs simulatio time. If you u the simulatio beyod this poit, the simulatio behaves upedictably. This limitatio is oly fo sim model.
  • The maco is ot available fo desigs with eabled auto-egotiatio ad lik taiig
  • You ca achieve faste simulatio times with auto-egotiatio ad lik taiig eabled desigs by uig i_ecofig_clk at 10GHz. Futhemoe, you ca skip auto-egotiatio ad lik taiig fuctioality ad go diectly to Data/Etheet mode by witig to auto-egotiatio ad lik taiig Cotol Status Registes (CSRs) o GUI paametes.
  • The maco appeas i the example desig simulatio scipts fo all the simulatos oly whe you select FGT, ad it is oly applicable fo FGT vaiats.

You ca also add the maco to you simulatio scipt fo you ow testbech.

Attetio: I 53G PAM4 Etheet IPs, you must set the seial clock iput to the IP to the exact value of 37.648 ps fo simulatio to wok coectly. This limitatio does ot apply to the desig example simulatios sice the seial lies ae i a loopback.
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