F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

Download PDF
ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

3.4. Hardware Design Example

Follow these steps to test Etheet-based desig examples with eabled PTP i hadwae:
  1. Geeate desig example as descibed i Geeatig the Desig.
  2. Set up the desig example hadwae test usig Agilex 7 I-Seies Tasceive-SoC Developmet Kit as descibed i Compilig ad Cofiguig the Desig Example i Hadwae.
  3. Lauch the Clock Cotol applicatio, which is pat of the developmet kit, ad set ew fequecies fo the desig example as descibed below. Below is the fequecy settig i the Clock Cotol applicatio.
    • Si5394, OUT3—156.25 MHz (i_efclk2pll)
    • Si5332, OUT1—125 MHz (i_clk_maste_tod)
    Note: The PHY efeece clock default value is 156.25 MHz. The ecofiguatio clock default value is 100 MHz.
  4. Iset the appopiate electic look back plug ito the Etheet pot.
  5. If you eabled Advaced Timestamp Accuacy Mode, geeate outig delay.
    • Afte successful compilatio, avigate to the <desig_example>/hadwae_test_desig diectoy.
    • Copy <desig_example>/ex_<speed>/eth_f_<vesio>/syth/eth_f_ptp_epot_dl_path_delay.tcl to the cuet diectoy.
    • Ru the scipt:
      quatus_sta -t eth_f_ptp_epot_dl_path_delay.tcl eth_f_hw
      The mai scipt souces the geeated ptp_hw_adv_adj.tcl fo outig delay adjustmet.
  6. Update the scipt with the loopback module's delay. This is a optioal step if timestamp accuacy is ot a coce.
    1. Ope the <desig_example>/hadwae_test_desig/hwtest/altea/ptp/ptp_paams.tcl file.
    2. Locate set PHY_DLY commad based o the <xcv_type> tasceive type ad the <apl> physical lae umbe. Fo example, the followig lie specifies the chael placed at top-most FGT lae:
      set PHY_DLY(lpbk_module_dly,0,15)
    3. Modify the <delay_value> delay value of loopback module chael. The default value is set to 0.
    Repeat steps b ad c fo all active chaels.
    Note: The tx_boad_dly ad x__boad_dly values povided i the ptp_paams.tcl file ae specific to the selected developmet kit. You must update these values, if you ae uig the scipt o a diffeet boad.
  7. Navigate to the <desig_example>/hadwae_test_desig/hwtest diectoy.
  8. Ope Tools > System Debuggig Tools > System Cosole.
  9. Ru the followig commad i the Tcl shell:
    souce mai_<Etheet_ate>_ptp.tcl
set_jtag<umbe_of appopiate_JTAG_maste>
  10. Ru the followig commad:
    u_test
    The test seds ad eceives 16 packets. The etie output file is available i the <desig_example>/hadwae_test_desig/hwtest/ptp_log.txt file.
The followig sample output illustates a successful hadwae test: 
--09:59:46-- Ifo: PTP Iitializatio begiig...  

Etheet Vaiat: 3 
ui:               0x004D19EC 
VL:               16 
PL_FL_MAP:        2 
tx_pma_delay_ui:  158 
x_pma_delay_ui:  175

#================================================= 
--09:59:46-- Ifo: Iitializig TX PTP fo IP_INST[0]  
=================================================#
--09:59:46-- Ifo: Wait fo TX PTP offset data valid assetio  
--09:59:46-- Ifo: TX PTP offset data valid asseted  
--09:59:46-- Ifo: Readig TX aw offset data  
--09:59:46-- Ifo: Detemie TX efeece lae  
            tx_ef_pl:               0x6 
            tx_am_actual_time_max:   0xd153f98
--09:59:46-- Ifo: Calculate TX offsets  
            tx_cost_delay:        0x9EE 
            tx_cost_delay_sig:   0x0 
            tx_ef_pl:             6 

(moe cotet …) 
-09:59:46-- Ifo:     TX PTP eady asseted.  
#================================================= 
--09:59:46-- Ifo: Iitializig RX PTP fo IP_INST[0]  
=================================================#
--09:59:46-- Ifo: Wait fo RX PCS fully aliged assetio  
--09:59:46-- Ifo:    50G to 400G FEC vaiat - RX PCS & RX FEC locked  
--09:59:46-- Ifo: FEC vaiat... poceed to x_fec_codewod_positio step

(moe cotet …)
--09:59:46-- Ifo: RX PTP eady asseted.  
--09:59:46-- Ifo: PTP Iitializatio completed!  
--09:59:46-- Ifo: Pogammig ASYM/P2P Registe fo demostatio  
             0x00000100 was witte to 0x10015044 
             Veifyig wite data by e-eadig 0x10015044 
             Addess 0x10015044 has value 0x100
            0x00000200 was witte to 0x10015048 
             Veifyig wite data by e-eadig 0x10015048 
             Addess 0x10015048 has value 0x200 
             0x00000200 was witte to 0x10025048 
             Veifyig wite data by e-eadig 0x10025048 
             Addess 0x10025048 has value 0x200 
--09:59:46-- Ifo: Pogammig ASYM/P2P Registe completed!  

--09:59:47-- Ifo: Checkig PTP packets  
--09:59:47-- Ifo: Wait fo TX Packet Valid to asset  
--09:59:47-- Ifo: TX Packet Valid detected  
--09:59:47-- Ifo: Readig TX Packets  

Fame moitoed by fame_pase TX 
Fame Legth : 128 
Empty : 0 
            ---------------------------------------------------------- 
                  |  00 01 02 03 04 05 06 07  08 09 10 11 12 13 14 15  
            ----------------------------------------------------------
            0000 |  AB E4 23 39 F0 00 1E 84  33 9F 01 00 88 F7 00 00
            0010 |  30 31 32 33 AA 35 36 AA  38 39 3A 3B 3C 3D 3E 3F
            0020 |  40 41 42 43 BB CC 46 47  48 49 4A 4B 4C 4D 4E 4F
            0030 |  50 51 52 53 54 55 56 57  BB CC 5A 5B 5C 5D 5E 5F
            0040 |  60 61 62 63 64 65 66 67  68 69 6A 6B 6C 6D 6E 6F
            0050 |  70 71 72 73 74 75 76 77  78 79 7A 7B 7C 7D 7E 7F
            0060 |  80 81 82 83 84 85 86 87  88 89 8A 8B 8C 8D 8E 8F
            0070 |  90 91 92 93 94 95 96 97  98 99 9A 9B 9C 9D 9E 9F
            ---------------------------------------------------------- 

--09:59:48-- Ifo: Readig PTP Commads  
--09:59:48-- Ifo: Readig TX PTP Commads  
--09:59:48-- Ifo: Readig TX Timestamps  
--09:59:48-- Ifo: Readig TX Egess Timestamp  
--09:59:48-- Ifo: Readig RX Timestamps  
--09:59:48-- Ifo: Wait fo RX Packet Valid to asset  
--09:59:48-- Ifo: RX Packet Valid detected  
--09:59:48-- Ifo: Readig RX Igess Timestamp  
--09:59:48-- Ifo: Readig RX Packets  
Fame moitoed by fame_pase RX 
Fame Legth : 128 
Empty : 0 
            ---------------------------------------------------------- 
                  |  00 01 02 03 04 05 06 07  08 09 10 11 12 13 14 15  
            ----------------------------------------------------------
            0000 |  AB E4 23 39 F0 00 1E 84  33 9F 01 00 88 F7 00 00
            0010 |  30 31 32 33 AA 35 36 AA  38 39 3A 3B 3C 3D 3E 3F
            0020 |  40 41 42 43 BB CC 46 47  48 49 4A 4B 4C 4D 4E 4F
            0030 |  50 51 52 53 54 55 56 57  BB CC 5A 5B 5C 5D 5E 5F
            0040 |  60 61 62 63 64 65 66 67  68 69 6A 6B 6C 6D 6E 6F
            0050 |  70 71 72 73 74 75 76 77  78 79 7A 7B 7C 7D 7E 7F
            0060 |  80 81 82 83 84 85 86 87  88 89 8A 8B 8C 8D 8E 8F
            0070 |  90 91 92 93 94 95 96 97  98 99 9A 9B 9C 9D 9E 9F
            ---------------------------------------------------------- 

------------------------------ 
TX PTP Commad #1 
------------------------------ 
Egess Timestamp Request            : 1 
Iset Timestamp                    : 0 
Update CoectioField              : 0 
Clea UDP/IPv4 Checksum             : 0 
Update UDP/IPv6 Exteded Bytes      : 0 
Add Pee-to-Pee (P2P) MiPathDelay : 0 
Add Asymmety Delay                 : 0 
Asymmety Delay Sig                : 0 
Asymmety & P2P MiPathDelay Select : 0x0 
Timestamp Field Offset              : 0x0000 
Coectio Field Offset             : 0x0000 
TX Figepit Data                 : 0x00000001 
TX Igess Timestamp                : 0x000000000024000000000000 
------------------------------ 
Timestamps #1 
------------------------------ 
TX Egess Timestamp                 : 0x0000000000241cb8ed9c6280 
RX Igess Timestamp                : 0x0000000000241cb8ed9d6c80 
TX Use Figepit                 : 0x00000001 
TX Retued Figepit             : 0x00000001 
------------------------------ 
Compaiso #1 
------------------------------ 
RX_ITS - TX_ETS       : 0x10a00/1.0391 s
TX Timestamp Fields   : 0x5051525354555657BBCC 
RX Timestamp Fields   : 0x5051525354555657BBCC
TX Coectio Fields  : 0x36AA38393A3B3C3D 
RX Coectio Fields  : 0x36AA38393A3B3C3D
Related Ifomatio
Level Two Title