F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.5. Compiling and Configuring the Design Example in Hardware

To compile the hadwae desig example ad cofigue it o you Itel device, follow these steps:
  1. Esue hadwae desig example geeatio is complete.
  2. I the Quatus® Pime Po Editio softwae, avigate to the Quatus® Pime poject diectoy eth_f_0_example_desig/hadwae_test_desig/.
  3. Ope the Quatus® Pime poject:
    quatus eth_f_hw.qpf &
  4. O the Pocessig meu, click Stat Compilatio.
  5. Afte successful compilatio, a .sof file is available i <desig_example_diectoy>/hadwae_test_desig/output_files.
    • Coect the Agilex 7 I-Seies Tasceive-SoC Developmet Kit to the host compute.
    • Lauch the Clock Cotolle applicatio, which is pat of the developmet kit.
      Figue 9. Clock Cotolle
      Set ew fequecies fo the desig example as followig:
      • Si5394 (U118), OUT3: Set to the value of i_efclk2pll 2 as 156.25MHz.
  6. O the Tools meu, click Pogamme.
  7. I the Pogamme, click Hadwae Setup.
  8. Select a pogammig device.
  9. Select ad add the Developmet Kit to which you Quatus® Pime Po Editio sessio ca coect.
  10. Esue that Mode is set to JTAG.
  11. Select the device ad click Add Device. The Pogamme displays a block diagam of the coectios betwee the devices o you boad.
  12. I the ow with you .sof, check the Pogam/Cofigue box fo the .sof file.
  13. Click Stat.
Note: If the System PLL fails to lock whe the i_efclk2pll fequecy is geate tha 156.25MHz, please efe to the steps specified i Why do F-tile Refeece ad System PLL clocks Itel® FPGA IP fail to lock at specific fequecies? to esolve the issue.
Related Ifomatio
2 The Clock Cotol GUI applicatio caot dive all the fequecies.
Level Two Title