F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.1.1. Generating Single IP Instance Design

Figue 2. Pocedue

  1. I the Quatus® Pime Po Editio, click File > New Poject Wizad to ceate a ew Quatus® Pime poject, o File > Ope Poject to ope a existig Quatus® Pime poject. The wizad pompts you to specify a device.
  2. Specify the device family Agilex™ 7 (F-Seies/I-Seies) ad select device with F-Tile fo you desig.
  3. Select Tools > IP Catalog to ope the IP Catalog ad select F-Tile Etheet Itel FPGA Had IP.
  4. Specify a top-level ame <you_ip> ad the folde fo you custom IP vaiatio. The paamete edito saves the IP vaiatio settigs i a file amed <you_ip> .ip.
  5. Click Ceate. The IP paamete edito appeas.
    Figue 3. Example Desig Tab
  6. O the IP tab, specify the paametes fo you IP coe vaiatio. Fo exact IP paamete settig, efe to the Selected IP Paamete Settigs table i the desied Desig Example chapte.
  7. Specify the paametes i the Example Desig tab.

Table 1.  Sigle Istace of IP Coe Desig Example Paametes
Paametes Value Desciptio
Select Desig

Sigle Istace of IP Coe

 Selects the sigle istace of IP coe fo example desig.
Example Desig Files

Simulatio

Sythesis

Eable Sigal Tap fo Debug
  • Simulatio optio geeates the testbech ad compilatio-oly poject.
  • Sythesis optio geeates the hadwae desig example.
  • Eable Sigal Tap fo Debug optio geeates a stadad sigal tap file. This optio is available oly fo a sigle IP istace ad whe AN/LT is disabled.
Simulatio Optios

Eable fast Simulatio

Eable Optimized Auto-Negotiatio ad Lik Taiig full simulatio

 Eables fast simulatio fo Etheet IP i geeated example desig. Whe AN/LT is eabled, It also eables the fast simulatio i AN/LT IP.

Eable Optimized Auto-Negotiati ad Lik Taiig full simulatio optio eables the optimized simulatio fo full auto-egotiatio ad lik taiig flow i geeated example desig. This optio caot be eabled alog with Eable Fast Simulatio.

Geeated File Fomat Veilog

VHDL

 Select the HDL files fomat. If you select VHDL, you must simulate the testbech with a mixed-laguage simulato.
Taget Developmet Kit Noe

Agilex™ 7 FPGA I-Seies Tasceive-SoC Developmet Kit (Poductio 1 4x F-Tile)

Agilex™ 7 FPGA I-Seies Tasceive-SoC Developmet Kit (ES 1 4x F-Tile)

Select Device Iitializatio Clock fo the Taget developmet kit optio specifies the taget developmet kit used to geeate the poject.

  1. Click the Geeate Example Desig butto.
The softwae geeates all desig files i sub-diectoies. You equie these files to u simulatio, compilatio, ad hadwae testig.
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