F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

3.2. Functional Description

Whe geeatig a desig example with PTP optio eabled, the softwae istatiates PTP-specific compoets.
Figue 13.  F-Tile Etheet Itel FPGA Had IP: Desig Example with Eabled PTP
The F-Tile Etheet Itel FPGA Had IP desig example icludes the followig compoets:
  • F-Tile Etheet Itel FPGA Had IP : Geeated IP coe with eabled PTP optio.
  • F-Tile Refeece ad System PLL Clocks Itel® FPGA IP : Istatiate efeece clock ad system PLL. Fo ifomatio about suppoted system PLL modes, efe to F-Tile Etheet Itel FPGA Had IP . Fo ifomatio about this IP, efe to F-Tile Achitectue ad PMA ad FEC Diect PHY IP Use Guide.
  • Time-of-Day (TOD): Povides a cotiuous flow of a cuet time-of-day ifomatio to the IP coe. The maste TOD us at 125 MHz clock fequecy. TX TOD ad RX TOD, which ae clocked by div66 o div68 clock of the F-Tile Etheet Itel FPGA Had IP, sychoize to the maste TOD though thei espective TOD sychoizes.

    Maste TOD also geeates a oe pulse pe secod (1 pps) to moito the accuacy ad allows sychoizatio betwee multiple devices.

    I this use guide, the geeated desig example assumes 0 ppm delay. I you desig, dive the maste TOD with the most accuate clock.

  • Packet Cliet: Cosists of multiple PTP elated modules. The Packet Cliet does ot suppot the PTP fuctioality whe packet loop back is set fom RX to TX i cliet side.
  • Packet Geeato: Cofigues to loop ove vaious pattes i the ROM. Alteatively, ca pefom a sigle tasmissio.
  • PTP Commad Geeato: The PTP commad geeatio module i the Packet Cliet geeates PTP commad fo the packet i tasmissio. The geeated commad aligs to stat-of-packet (SOP) fo Avalo® steamig iteface ad MAC segmeted based iteface.
  • Packet Moito: Stoes set ad eceived packet ifomatio betwee packet cliet ad the IP coe.
  • PTP Moito: The module stoes the PTP ifomatio set fom/to the Packet Cliet to/fom the F-Tile Etheet Itel FPGA Had IP whe packet loop backs fom TX seial to RX seial.
    Note: PTP Moito ca stoe ad ead 16 packets of 128 bytes i legth. Sedig moe packets without fist eadig the cotets of the PTP moito ca cause uexpected esults.
  • PTP Adapte Module ( Avalo® memoy-mapped iteface fo Asymmety ad Pee-to-Pee (P2P): If you eabled PTP optio i the F-Tile Etheet Itel FPGA Had IP, you must istatiate this module ad coect it to all associated Etheet IP coes. The desig allows oly oe istace pe tile.

    Whe istatiated, the module povides the access to the Avalo® memoy-mapped iteface egistes, specifically Asymmety Delay ad P2P MeaPathDelay egistes.

  • Avalo® memoy-mapped iteface Decode: Decodes the Avalo® memoy-mapped iteface addess to Hadwae IP Top, maste TOD, ad PTP adapte. Fo base addess fo each of the Avalo® memoy-mapped iteface accessed istaces, efe to Registe Maps.
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