F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

Download PDF
ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

4.5. Hardware Design Example

Follow these steps to test Etheet-based desig examples with eabled auto-egotiatio ad lik taiig i hadwae:
  1. Geeate desig example as descibed i Geeatig the Desig.
  2. Modify the .qsf settigs:
    • Set device to match the appopiate odeig pat umbe (OPN) fo you desig.
    • Update the piout to match the boad ad the desig fuctio.
    • Assig the appopiate VID settigs i you .qsf file to match you boad.
  3. Geeate the .sof file.
  4. Update boad clock settigs. The default value fo the PHY efeece clock is 156.25 MHz. The default value fo the ecofiguatio clock is 100 MHz.
  5. Iset appopiate electical loopback plug ito the Etheet pot.
  6. Pogam the desig.
  7. Ope Tools > System Debuggig Tools > System Cosole.
  8. Navigate to the hadwae diectoy <desig_example>/hadwae_test_desig/hwtest diectoy.
  9. Type souce mai_<vaiat_type>.tcl.
  10. Type set_jtag<umbe_of appopiate_JTAG_maste>
  11. Pefom this step if exteal loopback module is coected. Skip this step if the desig coects to lik pate.
    1. Type commad to ead the seq cfg egiste:
      eg_ead 0x101002C0
    2. Type commad to set the igoe oce value to 1:
      Note:
      • Fo Etheet modes (50GE-1, 100GE-2, ad 200GE-4) with FEC mode (Etheet Techology Cosotium RS(272, 258)), wite to 
        eg_wite 0x10100300 0x737d0381
      • Fo Etheet modes (25GE-1, 50GE-2, ad 400GE-8) with ay FEC mode, wite to 
        eg_wite 0x10100300 0x737d0381
      • Fo othe Etheet modes: 
        eg_wite 0x10100300 0x737d0281
    3. Type commad to estat the AN sequece:
      eg_wite 0x101002c0 0x00002003
    4. Type commad to ead the debug status:
      eg_ead 0x101003c0
      The lik is up if the commad etus value 1f0.
  12. Type the commad to check the PHY status:
    chkphy_status
  13. Type the commad to stat ad stop the packet geeato. The fuctio seds 16 packets.
    stat_pkt_ge
stop_pkt_ge
  14. Type the commad to check the MAC status:
    chkmac_stats

The followig sample output illustates a successful hadwae test:

% set_jtag 10
Cuetly selected maste is 10:
/devices/AGIB027R29AR(0|1|2|3)@1#USB-1#AGI FPGA Developmet kit#sj-appslaba-400.altea.piv.alta.com/(lik)/JTAG/(110:132 V1 #0)/phy_0/maste/chaels/local/mylib/maste_1
% eg_ead 0x101002c0
0xdeadc0de
% eg_ead 0x101002c0
0x00002002
% eg_ead 0x10100300
0x737d0201
% eg_wite 0x10100300 0x737d0281
0
% eg_ead 0x10100300
0x737d0281
% eg_wite 0x101002c0 0x2003
0
% eg_ead 0x101002c0
0x00002002
% eg_ead 0x101003c0
0x000001f0
% chkphy_status
RX PHY Registe Access: Checkig Clock Fequecies (KHZ)
       TXCLK   :40283 (KHZ)
       RXCLK   :40285 (KHZ)
TX PLL Lock Status        0x0000000f
Rx Fequecy Lock Status  0x0000000f
RX PCS Ready              0x1
TX laes Stable           0x1
Deskewed Status           0x1
Lik Fault Status         0x00000000
Rx Fame Eo            0x00000000
Rx Am LOCK Coditio      0x1

% stat_pkt_ge
0
% stop_pkt_ge
0
% Chkmac_stats
====================================================================
                      STATISTICS FOR BASE 12288 (Rx)
====================================================================
Fagmeted Fames              :0
Jabbeed Fames                :0
Ay Size with FCS E Fame    :0
Right Size with FCS E Fa    :0
Multicast data E Fames      :0
Boadcast data E Fames      :0
Uicast data E Fames        :0
Multicast Cotol E Fames   :0
Boadcast Cotol E Fames   :0
Uicast Cotol E Fames     :0
pause Cotol E Fames       :0
64 Byte Fames                 :0
65 - 127 Byte Fames           :32
128 - 255 Byte Fames          :1
256 - 511 Byte Fames          :0
512 - 1023 Byte Fames         :1
1024 - 1518 Byte Fames        :0
1519 - MAX Byte Fames         :0
> MAX Byte Fames              :0
Rx Fame States               :34
Multicast data OK Fame        :33
Boadcast data OK Fame        :0
Uicast Data OK Fame          :0
Multicast Cotol Fames       :0
Boadcast Cotol Fames       :0
Uicast Cotol Fames         :0
Pause Cotol Fames           :0
Data ad Paddig Octets        :2671
Fame Octets                   :3283
--------------------------------------------------------------------
====================================================================      
                      STATISTICS FOR BASE 12288 (Tx)
====================================================================
Fagmeted Fames              :0
Jabbeed Fames                :0
Ay Size with FCS E Fame    :0
Right Size with FCS E Fa    :0
Multicast data E Fames      :0
Boadcast data E Fames      :0
Uicast data E Fames        :0
Multicast Cotol E Fames   :0
Boadcast Cotol E Fames   :0
Uicast Cotol E Fames     :0
pause Cotol E Fames       :0
64 Byte Fames                 :0
65 - 127 Byte Fames           :32
128 - 255 Byte Fames          :1
256 - 511 Byte Fames          :0
512 - 1023 Byte Fames         :1
1024 - 1518 Byte Fames        :0
1519 - MAX Byte Fames         :0
> MAX Byte Fames              :0
Tx Fame States               :34
Multicast data OK Fame        :33
Boadcast data OK Fame        :0
Uicast Data OK Fame          :0
Multicast Cotol Fames       :0
Boadcast Cotol Fames       :0
Uicast Cotol Fames         :0
Pause Cotol Fames           :0
Data ad Paddig Octets        :2671
Fame Octets                   :3283
0
%
-------------------------------------------------------------------
Level Two Title