F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

2.2. Functional Description

Figue 10.  F-Tile Etheet Itel FPGA Had IP Simulatio Desig Example Block Diagam with FGT PMA

The F-Tile Etheet Itel FPGA Had IP desig example icludes the followig compoets:

  • F-Tile Etheet Itel FPGA Had IP : Geeated IP coe.
  • F-Tile Refeece ad System PLL Clocks Itel® FPGA IP : Istatiated efeece clock ad system PLL clock IP. The F-Tile Refeece ad System PLL Clocks Itel® FPGA IP paamete edito settigs alig with the System PLL fequecy ad PMA efeece fequecy paamete settigs i the F-Tile Etheet Itel FPGA Had IP. If you geeate the desig example usig Geeate Example Desig butto i the IP paamete edito, the IP istatiates automatically. If you ceate you ow desig example, you must maually istatiate this IP ad coect all I/O pots.

    Fo ifomatio about this IP, efe to F-Tile Achitectue ad PMA ad FEC Diect PHY IP Use Guide.

  • Packet Cliet: Cosists of a packet geeato, a packet checke ad a loopback cliet. The Packet Cliet geeates vaious ROM-based taffic pattes fo MAC mode ad ca loopback the RX ad TX cliet side.
  • Avalo® memoy-mapped iteface Decode: Decodes the Avalo® memoy-mapped iteface addess to Hadwae IP Top. Fo base addess fo each of the Avalo® memoy-mapped iteface accessed istaces, efe to Registe Maps.

Sectio Cotet
Vaiatio: F-Tile Etheet Itel FPGA Had IP with FHT PMA

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