F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

5.1. Features

  • Suppots multiple istatiatios of the same F-Tile Etheet Itel FPGA Had IP. Fo moe ifomatio, efe to the Available Numbe of Multiple IP Istaces pe Etheet Mode table.
  • Each istace suppots 10G, 25G, 40G, 50G, 100G, 200G, ad 400G Etheet ates
  • Each istace suppots Avalo® steamig iteface fo 10G, 25G, 40G, 50G, ad 100G Etheet ates with sychoized o asychoous adapte
  • Each istace suppots MAC segmeted iteface
  • Istatiates F-Tile Refeece ad System PLL Clocks Itel® FPGA IP based o Etheet cofiguatio
Whe you eable the multi istace IP optio, the desig example geeates multiple istaces of the same IP. The table specifies the umbe of istatiated F-Tile Etheet Itel FPGA Had IPs pe Etheet mode.
Table 16.  Available Numbe of Multiple IP Istaces pe Etheet Mode
Etheet Mode Modulatio PMA Type Numbe of Multiple IP Istaces
10GE-1 NRZ FGT 16
25GE-1 NRZ FGT 16
25GE-1 NRZ FHT 4
40GE-4 NRZ FGT 4
50GE-2 NRZ FGT 8
50GE-2 NRZ FHT 2
50GE-1 PAM4 FGT 8
50GE-1 PAM4 FHT 4
100GE-4 NRZ FGT 4
100GE-4 NRZ FHT 1
100GE-2 NRZ FGT 4
100GE-2 NRZ FHT 2
100GE-1 PAM4 FHT 4
200GE-8 NRZ FGT 2
200GE-4 PAM4 FGT 2
200GE-4 PAM4 FHT 1
200GE-2 PAM4 FHT 2
400GE-8 PAM4 FGT 1
400GE-4 PAM4 FHT 1
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