F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.2. Directory Structure

The F-Tile Etheet Itel FPGA Had IP coe desig example file diectoies cotai the followig geeated files fo the desig example.
Figue 7. Diectoy Stuctue fo F-Tile Etheet Itel FPGA Had IP Desig ExampleThe <etheet_mode> efes to the selected Etheet mode i the IP tab of the IP paamete edito.
Table 4.  Diectoy ad File Desciptio
Diectoy/File Desciptio
<desig_example_di>/hadwae_test_desig/eth_f_hw.qpf Quatus® Pime poject file.
<desig_example_di>/hadwae_test_desig/eth_f_hw.qsf Quatus® Pime settig file.
<desig_example_di>/hadwae_test_desig/eth_f_hw.v Desig example top-level HDL.
<desig_example_di>/hadwae_test_desig/eth_f_hw.sdc Syopsys Desig Costaits (SDC) file.
<desig_example_di>/hadwae_test_desig/commo Hadwae desig example suppot files. It also icludes a .stp file fo lik aalysis whe AN/LT ad the toolkit ae eabled. Refe to the Etheet Toolkit Use Guide fo details.
<desig_example_di>/hadwae_test_desig/hwtest/mai.tcl Mai file fo accessig System Cosole.
<desig_example_di>/hadwae_test_desig/eth_f_sigal_tap.stp Stadad Sigal Tap File.
Note: This optio is available oly fo a sigle IP istace ad whe AN/LT is disabled.
The Quatus® Pime softwae geeates the desig example files i the followig foldes:
  • <desig_example_di>/ex_<etheet_ate>G: IP coe files
  • <desig_example_di>/example_testbech: simulatio files fo testbech
  • <desig_example_di>/hadwae_test_desig: hadwae test desig files
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