F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

Documet Vesio Quatus® Pime Vesio IP Vesio Chages
2024.11.04 24.3 16.0.0 Made the followig chages:
  • Updated Select Device Iitializatio Clock fo the developmet kit paamete i Geeatig Sigle IP Istace Desig.
  • Updated the Example Desig IP GUI i the Geeatig Sigle IP Istace Desig.
  • Updated Select Device Iitializatio Clock fo the developmet kit paamete i Geeatig Two Sepaate Istaces of IP Desig sectio.
  • Updated the Example Desig IP GUI i the Geeatig Two Sepaate Istaces of IP Desigsectio.
  • Updated Select Device Iitializatio Clock fo the developmet kit paamete i the Geeatig Multiple IP Istace Desig sectio.
  • Updated the Example Desig IP GUI i theGeeatig Multiple IP Istace Desig sectio.
  • Updated theDiectoy Stuctue flow diagam.
  • Updated the desciptio fo <desig_example_di>/hadwae_test_desig/commo i the Diectoy Stuctue sectio.
  • Added <desig_example_di>/hadwae_test_desig/eth_f_sigal_tap.stp ad sigal tap file desciptio i the Diectoy Stuctue sectio.
  • Added istuctios to istatiate the I-system Souces & Pobes Itel® FPGA IP to geeate a sample Sigal Tap file fo ease of debuggig i the Featues sectio.
  • Updated the IP setup simulatio path i the Simulatio sectio of the Desig Example: Sigle IP Coe Istatiatio with AN/LT chapte.
  • Updated the IP setup simulatio path i the Simulatio sectio of the Desig Example: Two sepaate Istaces of AN/LT ad Etheet IP Desig chapte.
2024.07.09 24.2 15.0.0 Made the followig chages:
  • Coected the scipt commad fom chkmac_status to chkmac_stats to iitiate packet tasmissio fom the packet geeato to the IP coe i Testig the Hadwae Desig Example.
  • Added the followig compoet ames i the Fuctioal Desciptio topic ude the Desig Example: Sigle IP Coe Istatiatio with F-Tile Auto-Negotiatio ad Lik taiig sectio:
    • F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet
    • F-Tile Refeece ad System PLL Clocks
  • Coected the commad fom chkmac_status to chkmac_stats to check the MAC status i the Hadwae Desig Example topic ude the Desig Example: Sigle IP Coe Istatiatio with F-Tile Auto-Negotiatio ad Lik taiig sectio.
2024.04.01 24.1 14.0.0 Made the followig chages:
  • Updated Fast Sim Model fo FGT Vaiats.
  • Updated Fast Sim Model fo FHT Vaiats.
  • Updated Eable fast simulatio paamete desciptio i Sigle Istace of IP Coe Desig Example Paametes table.
  • Added a ote about whe you u the simulatio fo a multi-istace desig, the simulatio us by default i paallel. You eed to emove this maco fom the simulatio scipt
    +defie+PARALLEL_SIM
    i ode to u the seial simulatio, oe pot at a time.
2023.12.04 23.4 12.0.0 Made the followig chages:
  • Added commads to disable iteal loop back i Testig the Hadwae Desig Example.
  • Updated the bullet desciptio i Fast Sim Model fo FGT Vaiats.
  • Added the followig simulatio optios i the Example Desig IP tab.
    • Eable Fast Simulatio
    • Eable Optimized Auto Negotiatio ad lik Taiig full simulatio
2023.10.02 23.3 11.0.0 Updated a ote about the desig example simulatio scipt eables the maco by default fo all vaiats except fo the vaiats with PTP eabled i Fast Sim Model fo FHT Vaiats.
2023.04.03 23.1 9.0.0
  • Added ew sectio: Two sepaate istaces of Auto-Negotiatio ad Lik Taiig ad Etheet IP Desig
  • Added the followig topics i the Two sepaate istaces of Auto-Negotiatio ad Lik Taiig ad Etheet IP Desig.
    • Featues
    • Fuctioal Desciptio
    • Simulatio
    • QSF Assigmets
    • Hadwae Desig Example
  • Added a ote to the Testig the Hadwae Desig Example of the Quick Stat Guide sectio.
  • Updated the poduct family ame to "Itel Agilex 7."
2022.12.19 22.4 8.0.0 Made the followig chages:
  • Added Aldec Riviea-PRO simulato ad istuctio i Simulatig the Desig example Testbech.
  • Removed Geeatig Tile Files sectio.
  • Removed a ote about tile-elated files geeatio, desig_example_di>/ex_*G/sim, ad commad to u the IP setup simulatio i Simulatig the Desig Example Testbech.
  • Added ew topic: Fast Sim Model fo FHT Vaiats
  • Removed steps 5.a to 5.c to set fequecies fo the desig example i Compilig ad Cofiguig the Desig Example i Hadwae.
  • Updated step 4 bullets i Testig the F-Tile Etheet Itel FPGA Had IP Hadwae Desig Example.
    • iteal_loop_back_bk Istace_umbe o_of_laes
    • iteal_loop_back_bk Istace _umbe o_of_laes
  • Added a ote about tx_boad_dly ad x_boad_dly i step 6.c Hadwae Desig Example of Desig Example: Sigle IP Coe Istatiatio with Pecisio Time Potocol.
  • Added a ote i step 11.b i Hadwae Desig Example of Desig Example: Sigle IP Coe Istatiatio with Auto-Negotiatio ad Lik Taiig.
  • Updated steps to geeate tile-elated files fo successful simulatio i the Simulatio topic.
2022.09.26 22.3 7.0.0 Made the followig chages:
  • Added sceeshots fo successful AN/LT hadwae u i AN/LT Hadwae Desig Example.
  • Updated table 5: IP Paametes fo 100G Etheet Mode with 2 Laes Desig Example i Desig Example: Sigle IP Coe Istatiatio.
  • Added ote about PTP moito i fuctioal desciptio of Desig Example: Sigle IP Coe Istatiatio with Pecisio Time Potocol.
  • Added ote about auto-egotiatio ad lik taiig bodig suppot fo B0 FHT multi-lae desigs i fuctioal desciptio of Desig Example: Sigle IP Coe Istatiatio with Auto- Negotiatio ad Lik Taiig.
2022.06.20 22.2 6.0.0 Made the followig chages:
  • Added clock cotolle sceeshot ad updated steps i Compilig ad Cofiguig the Desig Example i Hadwae.
  • Updated Desig Example: Sigle IP Coe Istatiatio with Pecisio Time Potocol:

    Updated steps i Hadwae Desig Example.

  • Removed ote about i_ecofig_clk clock fequecy limitatio i Fuctioal Desciptio.
  • Added FGT ad FHT macos to simulatio u scipt fo AN/LT eabled desigs i simulatio.
2022.01.30 21.4 4.0.0
  • Added suppot fo the Xcelium* simulato.
  • Updated quick stat guide sub-sectios:
    • Globally added suppot fo the Agilex I-Seies Tasceive-SoC Developmet Kit.
    • Updated Geeatig Tile Files.
    • Added ew topic: Compilig ad Cofiguig the Desig Example i Hadwae.
    • Updated steps i Testig the F-Tile Etheet Itel FPGA Had IP Hadwae Desig Example.
  • Updated Desig Example: Sigle IP Coe Istatiatio with Pecisio Time Potocol:
    • Added ote about i_ecofig_clk clock fequecy limitatio.
    • Revised the sample output i the Simulatio sectio.
    • Added ew topic: Hadwae Desig Example.
  • Updated Desig Example: Sigle IP Coe Istatiatio with Auto-Negotiatio ad Lik Taiig:
    • Replaced the placemet assigmets with the colocate assigmets.
    • Updated simulatio flow.
    • Updated QSF assigmets.
2021.10.11 21.3 3.0.0
  • Added pi assigmet equiemet fo AN/LT desigs i Geeatig Tile Files.
  • Updated the list of suppoted simulatos i Simulatig the Desig Example Testbech.
  • Added ew topics:
    • Fast Sim Model
    • Testig the Hadwae Desig Example
    • Registe Maps
    • Simulatio Testbech Flow fo PCS, OTN, ad FlexE Modes
  • Updated egiste desciptios i Packet Cliet Registes.
  • Updated PTP-elated Registes sectio. Addess offset is specified as a byte addess.
  • Added ew desig examples: Sigle IP Coe Istatiatio with Auto-Negotiatio ad Lik Taiig
2021.07.01 21.2 2.0.0 Iitial elease.
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