F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

3.5. Registers

The PTP moito egistes ae pat of the Packet Cliet block of each Etheet IP istace. The Packet Cliet base addess fo each IP istace is available i Registe Maps.
Fo example, the PTP moito egistes addess i the thid Etheet IP istace is equivalet to 0x0210_0400, whee:
  • 0x0200_0000 is the Etheet IP: Istace 2 base addess
  • 0x0010_0000 is the Packet Cliet base addess fo the specified IP istace
  • 4*0x100 is the PTP moito base addess fo the specified IP istace
Table 12.  PTP Moito RegistesAll addess offsets ae specified i the wod addess fomat.
Wod Addess Name Bit Offset Default Value Access Desciptio
0x100 Soft Reset 0 1'b0 RW Soft eset fo PTP moito.

Pio to evey bust iteatio, you must wite 1'b1 followed by 1'b0.
0x101 TX_PKT_VALID 0 1'b0 RO
Idicates the TX packet data is available.
  • 0: No packet cotet is available fo ead out.
  • 1: Packet cotet is available.
TX_PTP_ETS_VALID 1 1'b0 RO
Idicates the TX egess timestamp is available.
  • 0: No timestamp is available fo ead out.
  • 1: Timestamp is available.
RX_PKT_VALID 2 1'b0 RO
Idicates the RX packet data is available.
  • 0: No packet cotet is available fo ead out.
  • 1: Packet cotet is available.
0x102 TX_PKT_DATA_63_32 [31:0] 32'h0 RO Idicates the TX packet data fo 64-bit segmet.
0x103 TX_PKT_DATA_31_0 [31:0] 32'h0 RO
0x104 TX_PKT_INFRAME 0 1'b0 RO Specifies TX packet ifame.
TX_PKT_SOP 1 1'b0 RO Idicates the stat-of-packet (SOP) fo TX packet.
TX_PKT_EOP 2 1'b0 RO Idicates the ed-of-packet (EOP) fo TX packet.
TX_PKT_EMPTY [5:3] 3'b000 RO Idicates that TX packet is empty.
TX_PKT_ERROR 6 1'b0 RO Idicates a TX packet eo.
TX_PKT_SKIP_CRC 7 1'b0 RO Idicates the settig of skip_cc sigal fo TX packet.
0x105 TX_PTP_TS_REQ 0 1'b0 RO Idicates a eceived equest fo TX PTP timestamp.
TX_PTP_INS_ETS 1 1'b0 RO Idicates TX PTP iset egess timestamp.
TX_PTP_INS_CF 2 1'b0 RO Idicates that TX PTP updated the Coectio Field with esidece time.
TX_PTP_ZERO_CSUM 3 1'b0 RO TX PTP clea checksum field fo IPv4 packet.
TX_PTP_UPDATE_EB 4 1'b0 RO Idicates that TX PTP updated exteded bytes fo IPv6 packets.
TX_PTP_P2P 5 1'b0 RO Idicates that TX PTP iseted pee-to-pee value fo MeaPathDelay sigal.
TX_PTP_ASYM 6 1'b0 RO Idicates that TX PTP iseted asymmety delay.
Reseved
TX_PTP_ASYM_SIGN 8 1'b0 RO Idicates the asymmety delay sig bit fo TX PTP packets.
TX_PTP_ASYM_PTP_IDX [15:9] 7'h0 RO TX PTP idex fom asymmety ad pee-to-pee lookup table.
TX_PTP_TS_OFFSET [31:16] 16'h0 RO Idicates the TX PTP timestamp offset.
0x106 TX_PTP_CF_OFFSET [15:0] 16'h0 RO Idicates offset fo the TX PTP CoectioField sigal.
TX_PTP_CSUM_OFFSET [31:16] 16'h0 RO Idicates offset fo the TX PTP ChecksumField sigal.
0x107 TX_PTP_USR_FP [31:0] 32'h0 RO Specifies you TX PTP figepit. The valid age depeds o the PTP_FP_WIDTH settig i the IP Paamete Edito.
0x108 TX_PTP_ITS_95_64 [31:0] 32'h0 RO Specifies the 96-bit TX PTP igess timestamp.
0x109 TX_PTP_ITS_63_32 [31:0] 32'h0 RO
0x10A TX_PTP_ITS_31_0 [31:0] 32'h0 RO
0x10C TX_PTP_ETS_FP [31:0] 32'h0 RO Specifies TX PTP figepit. The valid age depeds o the PTP_FP_WIDTH settig i the IP Paamete Edito.
0x10D TX_PTP_ETS_95_64 [31:0] 32'h0 RO Specifies the 96-bit TX PTP egess timestamp.
0x10E TX_PTP_ETS_63_32 [31:0] 32'h0 RO
0x10F TX_PTP_ETS_31_0 [31:0] 32'h0 RO
0x110 RX_PKT_INFRAME 0 1'b0 RO Specifies RX packet ifame.
RX_PKT_SOP 1 1'b0 RO Idicates the stat-of-packet (SOP) fo the RX packet.
RX_PKT_EOP 2 1'b0 RO Idicates the ed-of-packet (EOP) fo the RX packet.
RX_PKT_EMPTY [5:3] 3'b000 RO Idicates that RX packet is empty.
RX_PKT_ERROR [11:6]   RO Idicates a RX packet eo.
RX_PKT_FCS_ERROR 12 1'b0 RO Idicates a RX packet FCS eo.
0x111 RX_PKT_DATA_63_32 [31:0] 32'h0 RO Specifies the 64-bit segmet fo RX packet data.
0x112 RX_PKT_DATA_31_0 [31:0] 32'h0 RO
0x114 RX_PTP_ITS_95_64 [31:0] 32'h0 RO

Specifies the 96-bit RX PTP igess timestamp.
0x115 RX_PTP_ITS_63_32 [31:0] 32'h0 RO
0x116 RX_PTP_ITS_31_0 [31:0] 32'h0 RO
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