F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

5.3. Simulation

The testbech povides basic fuctioality such as the statup ad wait fo lock, sedig ad eceivig of a few packets pe each istatiated IP usig the ROM-based packet geeato.
Figue 17. Simulatio Desig Example Block Diagam with 2 istatiated F-Tile Etheet Itel FPGA Had IPs
The followig steps show the simulatio testbech flow:
  1. Asset global eset (i_st_) to eset each F-Tile Etheet Itel FPGA Had IP istace (IP istace).
  2. Wait util esets ackowledgmet fom all IP istaces. The o_st_ack_ sigals go low.
  3. Deassets the global eset.
  4. Wait util o_tx_laes_stable bit is set to 1, idicatig TX path is eady.
  5. Wait util o_x_pcs_eady bit is set to 1, idicatig RX path is eady.
  6. Repeat steps 4 ad 5 to complete the eset sequece fo all IP istaces.
  7. Istuct packet cliet to tasmit data. Wite hw_pc_ctl[0]=1'b1 to stat the packet geeato.
  8. Read TX packet data ifomatio fom 0x20 - 0x34 egistes. Read egistes i a sequetial ode.
  9. Read RX packet data ifomatio fom 0x38 - 0x4C egistes. Read egistes i a sequetial ode.
  10. Compae the coutes to esue 16 packets wee set ad eceived.
  11. Istuct packet cliet to stop data tasmissio. Wite hw_pc_ctl[2:0]=3'b100 to stop the packet geeato. Clea coutes.
  12. Repeat steps 7 - 11 to simulate packet tasfe fo each of the istatiated IPs.
  13. Pefom Avalo® memoy-mapped iteface test. Wite ad ead Etheet IP egistes.
  14. Pefom Avalo® memoy-mapped iteface 2 test to ead ad wite opeatio tasceive egistes.
  15. Repeat steps 13 ad 14 fo each istatiated IP i a sequetial ode.
Note: Whe you u the simulatio fo a multi-istace desig, the simulatio us by default i paallel. You eed to emove the followig maco fom the simulatio scipt i ode to u the seial simulatio, oe pot at a time. 
+defie+PARALLEL_SIM
The followig sample output illustates a successful simulatio test u. 
---SRC IP sequece stated -----
---SRC IP sequece TX completed -----
---SRC IP sequece RX completed -----
---Test    0;   ---Total     16 packets to sed-----
------Stat pkt ge TX-----
------Checkig Packet TX/RX esult-----
------------  16 packets Set;     0 packets Received--------
------ALL   16  packets Set out---
------------  16 packets Set;    16 packets Received--------
------ALL   16  packets Received---
------TX/RX packet check OK---
****Statig AVMM Read/Wite****
====>MATCH!     ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 
====>MATCH!     ReaddataValid = 1 Readdata = 00000007 Expected_Readdata = 00000007 
====>MATCH!     ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 
====>MATCH!     ReaddataValid = 1 Readdata = 9d228c3a Expected_Readdata = 9d228c3a 
====>MATCH!     ReaddataValid = 1 Readdata = 4338b586 Expected_Readdata = 4338b586 
====>MATCH!     ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 
====>MATCH!     ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 
====>MATCH!     ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 
====>MATCH!     ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 
====>MATCH!     ReaddataValid = 1 Readdata = 00000011 Expected_Readdata = 00000011 
====>MATCH!     ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee 
====>MATCH!     ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 
====>MATCH!     ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab 
743830s  Ty to access AVMM2 begi...
743830s  wite 0x00000065 to xcv  0 addess 0x103c004
744795s  Ty to access AVMM2 ed...
744890s  ead fom addess 0x103c004
====>MATCH!     ReaddataValid = 1 Readdata = 00000065 Expected_Readdata = 00000065 

...

758740s  Ty to access AVMM2 ed...
758840s  Ty to access AVMM2 begi...
758840s  wite 0x0000006c to xcv  7 addess 0x103c00b
759825s  Ty to access AVMM2 ed...
759920s  ead fom addess 0x103c00b
====>MATCH!     ReaddataValid = 1 Readdata = 0000006c Expected_Readdata = 0000006c 
760900s  Ty to access AVMM2 ed...
**** AVMM Read/Wite Opeatio Completed ****
** Testbech complete
**
Level Two Title