F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

5. Design Example: Multiple IP Core Instantiation

The multiple IP coe desig example demostates the ability to istatiate same F-Tile Etheet Itel FPGA Had IP multiple times i you desig.

The umbe of istatiated IP istaces depeds o the Etheet mode. Fo moe details, efe to Featues. To geeate the desig example, you must fist set the paamete values fo the IP coe vaiatio you ited to geeate i you ed poduct. Geeatig the desig example ceates multiple copies of you IP coe; the testbech desig example uses this vaiatio as the DUT. If you paamete values fo the DUT do't match the paamete values i you ed poduct, the desig example you geeate does ot execise the IP coe vaiatio you ited.

The multi IP coe desig example suppots PTP featue fo FGT PMA type.

The followig IP paamete settigs wee used to geeate this desig example:
Table 15.  IP Paametes fo 25G Etheet Mode with 1 Lae Desig ExampleTable specifies paamete settigs used to geeate this desig example.
Selected IP Paamete Settigs Value
IP Tab: Geeal Optios
PMA type FGT
Etheet mode 25GE-1
Cliet iteface MAC segmeted
FEC mode

IEEE 802.3 RS(528,514) (CL91)
PMA efeece fequecy 156.25
System PLL fequecy 805.664062
Example Desig Tab: Available Example Desigs
Select Desig Multi istace of IP coe

Fo moe ifomatio about steps o how to geeate a desig example, efe to the Geeatig the Desig Example.


Sectio Cotet
Featues
Fuctioal Desciptio
Simulatio

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