F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.3
IP Version 16.0.0
The F-Tile Etheet Itel® FPGA Had IP coe povides a simulatio testbech ad a hadwae desig example that suppots compilatio ad hadwae testig. Whe you geeate the desig example, the paamete edito automatically ceates a example desig with all files ecessay to compile ad test the desig i hadwae. The simulatio example desig cotais a simple testbech used to execise the hadwae example desig.

You ca geeate a desig example fo ay suppoted vaiats icludig desig examples with Media Access Cotolle (MAC) iteface, Physical Codig Sublaye (PCS) iteface, Optical Taspot Netwok (OTN) iteface, ad Flexible Etheet (FlexE) iteface fo vaious Etheet modes ad optioal FEC mode. I you desig example, you ca also eable the Pecisio Time Potocol (PTP) ad auto-egotiatio ad lik taiig optios. Fo a list of suppoted cofiguatios i the cuet Quatus® Pime Po Editio softwae vesio, efe to the Vaiat Selectio table i the F-Tile Etheet Itel FPGA Had IP Use Guide.

This use guide descibes the followig desig examples:
Note: The cuet Quatus® Pime Po Editio softwae elease does ot suppot 40GE/50GE/100GE OTN desig examples with o FEC.
Figue 1. Developmet Stages fo the Desig ExampleFutue IP coe eleases also povide a hadwae desig example you ca compile ad test i hadwae.

Sectio Cotet
Geeatig the Desig
Diectoy Stuctue
Simulatig the Desig Example Testbech
Hadwae ad Softwae Requiemets
Compilig ad Cofiguig the Desig Example i Hadwae
Testig the F-Tile Etheet Itel FPGA Had IP Hadwae Desig Example
Registe Maps

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