F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.3. Simulating the Design Example Testbench

You ca compile ad simulate the desig by uig a simulatio scipt fom the commad pompt.
Figue 8. Pocedue
  1. At the commad pompt, chage the wokig diectoy to <desig_example_di>/example_testbech.
  2. Ru the simulatio scipt fo the suppoted simulato of you choice. The scipt compiles ad us the testbech i the simulato. Refe to the table Steps to Simulate the Testbech.
  3. Aalyze the esults. The successful testbech displays "Simulatio Passed".
    Table 5.  Steps to Simulate the Testbech
    Simulato Istuctios
    Syopsys* VCS* I the commad lie, type: 
    sh u_vcs.sh
    Syopsys* VCS* MX I the commad lie, type: 
    sh u_vcsmx.sh

    Use this scipt whe the desig cotais Veilog HDL ad System Veilog with VHDL.
    ModelSim* SE o QuestaSim* o Questa* Itel® FPGA Editio I the commad lie, type:
    vsim -do u_vsim.do
    If you pefe to simulate without bigig up the GUI, type: 
    vsim -c -do u_vsim.do
    Xcelium* I the commad lie, type:
    sh u_xcelium.sh
    Aldec Riviea-PRO* 1 I the commad lie, type 
    vsim -c -do u_ivieasim.do
A successful simulatio eds with the followig message: 
Simulatio Passed.
o 
Testbech complete.
Afte successful completio, you ca aalyze the esults.

Sectio Cotet
Fast Sim Model fo FGT Vaiats
Fast Sim Model fo FHT Vaiats

1 Oly Riviea 2022.10 is suppoted
Level Two Title