F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.7. Register Maps

This sectio displays the available egiste addess age fo F-Tile Etheet Itel FPGA Had IP ad F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IPs.
The F-Tile Etheet Itel FPGA Had IP suppots up to 16 Etheet IP istaces. The addess age fo each IP istace is show i the Registe Map fo Multi-Rate IP Istaces, PTP, ad AN/LT table. The table also displays the addess age fo PTP-elated blocks ad auto-egotiatio ad lik taiig (AN/LT).
Note: The PTP ad AN/LT addess age is the same egadless of whethe the PTP ad AN/LT featues ae eabled o ot.
Table 6.  Registe Map fo Multi-Istace IP Desig Examples, PTP, ad AN/LT The addess age is specified as a byte addess.
Addess Rage [28:0] Module
0x0000_0000 - 0x00FF_FFFC Etheet IP : Istace 0
0x0100_0000 - 0x01FF_FFFC Etheet IP : Istace 1
0x0200_0000 - 0x02FF_FFFC Etheet IP : Istace 2
0x0300_0000 - 0x03FF_FFFC Etheet IP : Istace 3
0x0400_0000 - 0x04FF_FFFC Etheet IP : Istace 4
0x0500_0000 - 0x05FF_FFFC Etheet IP : Istace 5
0x0600_0000 - 0x06FF_FFFC Etheet IP : Istace 6
0x0700_0000 - 0x07FF_FFFC Etheet IP : Istace 7
0x0800_0000 - 0x08FF_FFFC Etheet IP : Istace 8
0x0900_0000 - 0x09FF_FFFC Etheet IP : Istace 9
0x0A00_0000 - 0x0AFF_FFFC Etheet IP : Istace 10
0x0B00_0000 - 0x0BFF_FFFC Etheet IP : Istace 11
0x0C00_0000 - 0x0CFF_FFFC Etheet IP : Istace 12
0x0D00_0000 - 0x0DFF_FFFC Etheet IP : Istace 13
0x0E00_0000 - 0x0EFF_FFFC Etheet IP : Istace 14
0x0F00_0000 - 0x0FFF_FFFC Etheet IP : Istace 15
0x1000_0000 - 0x1000_FFFC PTP Maste TOD egistes
0x1001_5000 - 0x1001_5FFC PTP Adapte: Asymmety Delay
0x1002_5000 - 0x1002_5FFC PTP Adapte: Pee-to-Pee MeaPathDelay
0x1003_0000 - 0x100F_FFFC Reseved
0x1010_0000 - 0x101F_FFFC Auto-egotiatio ad lik taiig: Istace 0
0x1020_0000 - 0x102F_FFFC Auto-egotiatio ad lik taiig: Istace 1

The table below displays the egiste addess map withi a sigle Etheet IP istace.

Table 7.  Registe Addess Map fo Sigle Etheet IP IstaceThe addess age is specified as a byte addess.
Addess Rage [28:0] Module
0x0000_0000 - 0x0000_FFFC Etheet ecofiguatio iteface
0x0001_0000 - 0x000F_FFFC Reseved
0x0010_0000 - 0x007F_FFFC Packet Cliet
0x0080_0000 - 0x008F_FFFC Tasceive ecofiguatio iteface fo lae 0
0x0090_0000 - 0x009F_FFFC Tasceive ecofiguatio iteface fo lae 1
0x00A0_0000 - 0x00AF_FFFC Tasceive ecofiguatio iteface fo lae 2
0x00B0_0000 - 0x00BF_FFFC Tasceive ecofiguatio iteface fo lae 3
0x00C0_0000 - 0x00CF_FFFC Tasceive ecofiguatio iteface fo lae 4
0x00D0_0000 - 0x00DF_FFFC Tasceive ecofiguatio iteface fo lae 5
0x00E0_0000 - 0x00EF_FFFC Tasceive ecofiguatio iteface fo lae 6
0x00F0_0000 - 0x00FF_FFFC Tasceive ecofiguatio iteface fo lae 7

Fo example, the Packet Cliet base addess i the 2d Etheet IP istace is equivalet to 0x0100_0000 + 0x0010_0000 = 0x0110_0000.

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