F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes

The followig steps show the simulatio testbech flow fo PCS, OTN, ad FlexE modes:
  1. Asset global eset (i_st_) to eset the F-Tile Etheet Itel FPGA Had IP.
  2. Wait util esets ackowledgmet. The o_st_ack_ sigal goes low.
  3. Deassets the global eset.
  4. Wait util o_tx_laes_stable bit is set to 1, idicatig TX path is eady.
  5. Wait util o_x_pcs_eady bit is set to 1, idicatig RX path is eady.
    Note: I o-MAC mode, the packet cliet seds out idle data i MII/PCS66 fomat.
  6. Read TX packet data ifomatio fom 0x00 - 0x34 egistes i sequetial ode.
    • 0x00: Set hw_pc_ctl[6] = 1'b1 to eable sapshot bit to ead the TX packet statistics.
    • 0x020/0x24: TX stat of packet coute (LSB/MSB)
    • 0x28/0x2C: TX ed of packet coute (LSB/MSB)
    • 0x00: Set hw_pc_ctl[6] = 1'b0 to disable sapshot bit.
  7. Read RX packet data ifomatio fom 0x38 - 0x4C egistes i sequetial ode.
    • 0x00: Set hw_pc_ctl[6] = 1'b1 to eable sapshot bit to ead the RX packet statistics.
    • 0x38/0x3C: RX stat of packet coute (LSB/MSB)
    • 0x40/0x44: RX ed of packet coute (LSB/MSB)
    • 0x48/0x4C: RX eo coute (LSB/MSB)
    • 0x00: Set hw_pc_ctl[6] = 1'b0 to disable sapshot bit.
  8. Compae the coutes to esue 16 packets wee set ad eceived.
  9. Istuct packet cliet to stop data tasmissio. Wite cfg_stat_pkt_ge[0]=1'b1 to stop the packet geeato. Clea coutes.
  10. Pefom Avalo® memoy-mapped iteface test. Wite ad ead Etheet IP egistes.
    • 0x104: Scatch egiste
    • 0x108: Etheet IP soft eset egiste
    • 0x004: Etheet IP debug cofiguatio cotol egiste
    • 0x008: Etheet IP eable/clock gatig cofiguatio egiste
  11. Pefom Avalo® memoy-mapped iteface 2 test. Wite ad ead tasceive egistes.
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