F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

Download PDF
ID 683804
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example

Afte you compile the F-Tile Etheet Itel FPGA Had IP coe desig example ad cofigue it o you Agilex™ 7 device, you ca use the System Cosole to pogam the IP coe.

Follow these steps to test the hadwae desig example o the System Cosole:
  1. Navigate to the hadwae diectoy: <desig_example>/hadwae_test_desig/hwtest.
  2. Ope Tools > System Debuggig Tools > System Cosole o type commad:
    system-cosole &
  3. Ru the followig commads i the System Cosole Tcl shell. 
    souce mai_<Etheet_ate>.tcl
set_jtag<umbe_of appopiate_JTAG_maste>
    Note:
    • The set_jtag commad places the Agilex™ 7 device o the JTAG chai
    • If you do ot wat to use eset whe selectig jtag, use set_jtag_o_eset
    Note: If you eabled auto-egotiatio ad lik taiig i you desig, follow the hadwae desig example steps descibed i Hadwae Desig Example.
  4. Ru oe of the followig commads.
    • If you use the iteal seial loopback, ete 
      u_test
    • If you iseted a exteal loopback plug ito the desied Etheet pot, ete 
      u_test_without_loopback
The hadwae desig example uses u_test commad to iitiate packet tasmissio fom packet geeato to the IP coe. Specifically, the scipt pefoms the followig steps:
  • chkphy_status: Displays the clock fequecies ad PMA PHY lock status.
  • chkmac_stats: Displays the MAC statistics coutes.
  • clea_all_stats: Cleas the IP coe statistics coutes.
  • stat_pkt_ge: Stats the packet geeato.
  • stop_pkt_ge: Stops the packet geeato.
  • iteal_loop_back_bk Istace_umbe o_of_laes: Eables the iteal loop back fo FHT vaiat.
  • iteal_loop_back_ux Istace_umbe ip_base_add o_of_laes lae_x lae_y: Eables the iteal loop back fo FGT vaiat.
Note: Use the followig commads to disable the iteal loop back:
  • disable_loop_back_ux o_of_laes 0 2: Disables the iteal loop back fo FGT vaiat lae 1
  • disable_loop_back_ux o_of_laes 3 2: Disables the iteal loop back fo FGT vaiat lae 2,4, ad 8
  • disable_loop_back_bk o_of_laes
The followig sample output illustates a successful hadwae test u: 
% u_test_without_loopback
--- Tuig off packet geeatio ----
--------------------------------------
--- Wait fo RX clock to settle... ---
--------------------------------------
-------- Pitig PHY status ---------
--------------------------------------
 RX PHY Registe Access: Checkig Clock Fequecies (KHz) 
	TXCLK 		:41505  (KHZ) 
	RXCLK 		:41503  (KHZ) 

 TX PLL Lock Status           0x000000ff
 RX Fequecy Lock Status     0x000000ff
 RX PCS Ready                 0x00000001
 TX Laes Stable              0x00000001
 Deskew status                0x00000001 
 Lik Fault Status            0x00000000
 RX Fame Eo               0x00000000
 RX AM LOCK Coditio         0x00000001 

---- Cleaig MAC stats coutes -----
---- Iitialize PKT ROM Read addess fo IP_INST[0] ----
--------------------------------------
--------- Sedig packets... ---------
--------------------------------------
----- Readig MAC stats coutes -----
--------------------------------------

==========================================================================================
                        STATISTICS FOR BASE 20480 (Rx)                               
 ==========================================================================================
Fagmeted Fames                : 0 
Jabbeed Fames                  : 0 
Ay Size with FCS E Fame      : 0 
Right Size with FCS E Fa      : 0 
Multicast data  E Fames       : 0 
Boadcast data E  Fames       : 0 
Uicast data E  Fames         : 0 
Multicast cotol  E Fame     : 0 
Boadcast cotol E  Fame     : 0 
Uicast cotol E  Fames      : 0 
Pause cotol E  Fames        : 0 
64 Byte Fames                   : 0 
65 - 127 Byte Fames             : 16 
128 - 255 Byte Fames            : 0 
256 - 511 Byte Fames            : 0 
512 - 1023 Byte Fames           : 0 
1024 - 1518 Byte Fames          : 0 
1519 - MAX Byte Fames           : 0 
> MAX Byte Fames                : 0 
Rx Fame Stats                  : 16
Multicast data  OK  Fame        : 16
Boadcast data OK   Fame        : 0 
Uicast data OK   Fames         : 0
Multicast Cotol Fames         : 0 
Boadcast Cotol Fames         : 0 
Uicast Cotol Fames           : 0 
Pause Cotol Fames             : 0
Data ad paddig octets          : 800
Fame octets:                    : 1088
==========================================================================================
                        STATISTICS FOR BASE 20480 (Tx)                               
 ==========================================================================================
Fagmeted Fames                : 0 
Jabbeed Fames                  : 0 
Ay Size with FCS E Fame      : 0
Right Size with FCS E Fa      : 0 
Multicast data  E Fames       : 0 
Boadcast data E  Fames       : 0 
Uicast data E  Fames         : 0 
Multicast cotol  E Fame     : 0 
Boadcast cotol E  Fame     : 0 
Uicast cotol E  Fames      : 0 
Pause cotol E  Fames        : 0 
64 Byte Fames                   : 0
65 - 127 Byte Fames             : 16
128 - 255 Byte Fames            : 0 
256 - 511 Byte Fames            : 0 
512 - 1023 Byte Fames           : 0 
1024 - 1518 Byte Fames          : 0 
1519 - MAX Byte Fames           : 0 
> MAX Byte Fames                : 0 
Tx Fame Stats                  : 16 
Multicast data  OK  Fame        : 16
Boadcast data OK   Fame        : 0 
Uicast data OK   Fames         : 0 
Multicast Cotol Fames         : 0 
Boadcast Cotol Fames         : 0 
Uicast Cotol Fames           : 0 
Pause Cotol Fames             : 0
Data ad paddig octets          : 800
Fame octets:                    : 1088
------------ Doe ---------------------
Note: Clock fequecy eadout must be scaled fo display, if i_ecofig _clk is ot 100MHz. Fo example, if i_ecofig _clk is 250MHz, the display should be scaled by x 2.5.
Related Ifomatio
Level Two Title