Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

SETUP_HOLD_TIME_VIOLATION_DETECTION

Enables setup and hold time violation detection during simulation.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax

set_instance_assignment -name SETUP_HOLD_TIME_VIOLATION_DETECTION -to <to> -entity <entity name> <value>