Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

ENABLE_STATE_MACHINE_INFERENCE

Allows the Compiler to infer state machines from Verilog/Vhdl Design Files. The Compiler optimizes state machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler extracts and optimizes state machines in Verilog/VHDL Design Files as regular logic.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Analysis & Synthesis report.

Syntax

set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE <value>

Default Value

On

Example

set_global_assignment -name enable_state_machine_inference on