Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

SYNTH_GATED_CLOCK_CONVERSION

Automatically converts gated clocks in the design to use clock enable pins if clock enable pins are not used in the original design. Clock gating logic can contain AND, OR, MUX, and NOT gates, as well as latch or FF-based synchronizers. Turning on this option may increase memory use and overall run time. You must additionally use the Gated Clock Conversion Base Clock assignment to specify which base clocks to do gated clock conversion on.

Type

Boolean

Device Support

  • Intel Agilex® 5
  • Intel Agilex® 7
  • Arria® 10
  • Cyclone® 10 GX
  • Stratix® 10

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION -entity <entity name> <value>
set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION -to <to> -entity <entity name> <value>
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION <value>

Default Value

Off

Example

set_global_assignment -name synth_gated_clock_conversion on
set_instance_assignment -name synth_gated_clock_conversion on -to foo