Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS

Specifies the maximum number of worst-case timing paths for the Timing Analyzer to report per clock domain and analysis.

Old Name

TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS

Type

Integer

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

INTEGER_RANGE

1, 100000

Notes

None

Syntax

set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS <value>

Default Value

10