Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

EDA_EXTRA_VERILOG_COMPILE_OPTION_FOR_NON_IP

Additional custom compilation options for one or more simulators to be applied on the Non-IP Verilog RTL. E.g. questa=my_questa_options : vcs=my_vcs_options : vcsmx=my_vcsmx_options : activehdl=my_activehdl_options : xcelium=my_xcelium_options : rivierapro=my_activehdl_options

Type

String

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

The value of this assignment is case sensitive.

This assignment is included in the Fitter report.

Syntax

set_global_assignment -name EDA_EXTRA_VERILOG_COMPILE_OPTION_FOR_NON_IP -section_id <section identifier> <value>
set_global_assignment -name EDA_EXTRA_VERILOG_COMPILE_OPTION_FOR_NON_IP -entity <entity name> -section_id <section identifier> <value>

Default Value

, requires section identifier