Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

OUTPUT_PIN_LOAD

Specifies the capacitive load, in picofarads (pF), on output pins for each I/O standard. Note: These settings affect FPGA pins only. To specify board trace, termination, and capacitive load parameters for use with Advanced I/O Timing, use the Board Trace Model tab. Capacitive loading is ignored if applied to anything other than an output or bidirectional pin, or if Advanced I/O Timing is enabled.

Type

Integer

Device Support

  • Intel Agilex® 5
  • Intel Agilex® 7

INTEGER_RANGE

0, 10000

Notes

This assignment is copied to any duplicated nodes.

Syntax

set_instance_assignment -name OUTPUT_PIN_LOAD -to <to> -entity <entity name> <value>
set_global_assignment -name OUTPUT_PIN_LOAD -section_id <section identifier> <value>