Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

HDL_INITIAL_FANOUT_LIMIT

Directs Integrated Synthesis to check the initial fan-out of each net in the netlist immediately after elaboration but prior to any netlist optimizations. If the fan-out for a net exceeds the specified limit, then Integrated Synthesis will issue a warning.

Type

Integer

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name HDL_INITIAL_FANOUT_LIMIT -entity <entity name> <value>
set_instance_assignment -name HDL_INITIAL_FANOUT_LIMIT -to <to> -entity <entity name> <value>

Example

set_instance_assignment -name hdl_initial_fanout_limit 100 -to foo