Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

SDC_STATEMENT

Specifies the SDC statement to be evaluated by the Timing Analyzer. Any collection filters used in the entity bound SDC have a global scope (evaluated in reference to the root of the design).

Type

String

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

The value of this assignment is case sensitive.

Syntax

set_global_assignment -name SDC_STATEMENT -entity <entity name> <value>

Example

set_global_assignment -name sdc_statement "set_multicycle_path -setup 2 -from *|mod_one -to *|mod_two" -entity "my_module"