Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

EDA_MAP_ILLEGAL_CHARACTERS

Maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus Prime hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, in Verilog Output Files. Turning on this option also maps other illegal non-alphanumeric characters, including brackets [], parentheses, (), angle brackets <>, and braces {} to underscores (_).

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Fitter report.

Syntax

set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -section_id <section identifier> <value>
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -entity <entity name> -section_id <section identifier> <value>

Default Value

Off, requires section identifier