Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

EDA_VHDL_ARCH_NAME

Specify the name of Architecture in the generated VHDL simulation netlist.

Type

String

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

The value of this assignment is case sensitive.

This assignment is included in the Fitter report.

Syntax

set_global_assignment -name EDA_VHDL_ARCH_NAME -section_id <section identifier> <value>

Default Value

structure, requires section identifier