Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

RTLV_SIMPLIFIED_LOGIC

Allow RTL Viewer to remove wire nodes and merge chain of equivalent combinatorial gates

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax

set_global_assignment -name RTLV_SIMPLIFIED_LOGIC <value>

Default Value

On