Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

EDA_WRITE_DEVICE_CONTROL_PORTS

Add the devpor, devclrn, and devoe signals in the design as input ports in the top-level design hierarchy in the Verilog or VHDL simulation netlist for the project.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

This assignment is included in the Fitter report.

Syntax

set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -section_id <section identifier> <value>
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -entity <entity name> -section_id <section identifier> <value>

Default Value

Off, requires section identifier